después de la síntesis en xilinx vivado, recibo la ADVERTENCIA:
[Synth 8-5788] El registro next_state_reg en el módulo example_code se establece y se reinicia con la misma prioridad. Esto puede causar desajustes de simulación. Considere reescribir el código.
¿Por qué recibo esta advertencia y cómo resolverla sin cambiar la lógica en el ejemplo de código siguiente?
always @(posedge clk or posedge rst)
begin
if(rst)
state <= a;
else
state <= next_state;
end
always @(posedge clk or posedge rst)
begin
if(rst)begin
count = 1;
wt_refresh = 0;
end
else begin
case(state)
a: begin
wt_refresh = 0;
if(in_put)
count = count;
else if(count < hold*30)
count = count+1;
else begin
count = 1;
next_state = b;
wt_refresh = 1;
end
end
b: begin
wt_refresh = 0;
if(in_put)begin
count = 1;
next_state = a;
wt_refresh = 1;
end
else begin
if(count != 20)
count = count+1;
else begin
count = 1;
next_state = c;
wt_refresh = 1;
end
end
end
c: begin
wt_refresh = 0;
if(in_put)
count = count;
else if(count < hold*15)
count = count+1;
else begin
count = 1;
next_state = d;
wt_refresh = 1;
end
end
d: begin
wt_refresh = 0;
if(in_put)begin
count = 1;
next_state = a;
wt_refresh = 1;
end
else begin
if(count != 20)
count = count+1;
else begin
count = 1;
next_state = e;
wt_refresh = 1;
end
end
end
e: begin
wt_refresh = 0;
if(in_put)begin
count = 1;
next_state = a;
wt_refresh = 1;
end
else
next_state = e;
end
endcase
end
end