Todavía soy un principiante y sigo recibiendo este error, ¿alguien puede ayudar a los pls?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity ClkDivider is
port ( clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out : out STD_LOGIC);
end ClkDivider;
architecture behaviour of ClkDivider is
signal counter: integer := 0;
signal temporal: integer range 0 to 499 := 0;
begin
clock_divider: process (reset, clk_in)
begin
if (reset = '1') then
temporal <= 0;
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 499) then
temporal <= not (temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end behaviour;