Valor del registro que va a alta impedancia después del restablecimiento en la simulación posterior a la síntesis (Vivado 2016.4)

En la simulación posterior a la síntesis, el valor del registro "estado" es '0' cuando la señal de reinicio es '1'. Pero, cuando la señal de reinicio llega a cero, el valor del registro "estado" va a una impedancia alta. El registro "estado" se mantuvo en cero en la simulación previa a la síntesis. Entonces, ¿cuál podría ser el posible error que estoy haciendo? Estoy tratando de implementar el protocolo i2c en xilinx fpga.

MasterClock: 100MHz, divclock: 100kHz, sdaclock: 100KHz (divclock wrt de fase desplazada en un módulo separado) (Funciona en correos                   simulación de síntesis)

'timescale 1ns / 1ps

module i2c_sensor(
input masterclock,
input div_clock,
input sdaclock,
output scl1,
inout data,
input start,
input reset,
output [12:0] tempout
);
reg scl;
reg sda;
reg scl_enable;
reg [3:0] state;
parameter i2c_idle=0;
parameter i2c_start1=1;
parameter i2c_slaveaddress1=2;   //write mode
parameter i2c_configreg1=3;    
parameter i2c_start2=4;
parameter i2c_slaveaddress2=5;   //read mode
parameter i2c_tempdetect=6;    
parameter i2c_stop2=7;
parameter i2c_idle2=8;




//registers
reg [12:0] temperature;
reg [7:0] count;
reg [7:0] count2;
reg [7:0] slaveregwrite;
reg [7:0] slaveregread;
reg [7:0] configuration_register;


always@(posedge masterclock)
begin
if(scl_enable==0)
scl<=1;
else
scl<=div_clock;
end
// assign scl = (scl_enable==0)?1:div_clock;
always@(posedge sdaclock,posedge reset)
begin
if(reset)begin
state<=i2c_idle;
slaveregwrite<=8'h96;
slaveregread<=8'h97;
configuration_register<=8'h1C;
scl_enable <= 0;
sda<=1;
count<=0;
count2<=0;
temperature<=0;
end
else  begin

if(state!=4'b0000 || state!=4'b0001 || state!=4'b0100 || state!=4'b0111 || 
state!=4'b1000)
    scl_enable <= 1;
    else
    scl_enable <= 0;


case(state)
i2c_idle :          begin
                    sda<=1;
                    if(start)
                    state<=i2c_start1;
                    end

i2c_start1 :        begin
                    sda<=0;
                    count<=7;
                    state=i2c_slaveaddress1;
                    end

i2c_slaveaddress1 : begin    
                    sda<=slaveregwrite[count];                       //slave 
address and write mode(even address)
                    if(count!=0)
                    begin
                    count = count-1;
                    end
                    else
                    begin
                    state<=i2c_configreg1;
                    count<=7;
                    count2<=1;
                    end
                    end

i2c_configreg1 :    begin
                    if(count!=0)
                    begin
                    sda<=configuration_register[count];
                    count<=count-1;
                    end
                    else begin
                    if(count2==0)
                    state<=i2c_idle2;
                    else 
                    count2<=count2-1;
                    count<=1;
                    end
                    end

i2c_idle2 :         begin
                    sda<=1;
                    if(count!=0)
                    begin
                    count<=count-1;
                    end
                    else
                    state<=i2c_start2;
                    end                    
i2c_start2 :        begin
                    sda=0;                      //sending start sequence 
again
                    state<=i2c_slaveaddress2;
                    count<=7;
                    end

i2c_slaveaddress2:  begin

                      //slave address and read mode(odd address)
                    if(count!=0)
                    begin
                    sda<=slaveregread[count];
                    count <= count -1;
                    end
                    else
                    begin
                    state<=i2c_tempdetect;
                    count<=12; end
                    end

i2c_tempdetect:     begin
                    //scl<=clock;
                    if(count)
                    begin
                    temperature[count]<=sda;
                    count <= count-1;
                    end
                    else 
                    sda<=0;
                    state <= i2c_stop2;
                    end 

i2c_stop2:          begin
                    sda<=1;
                    state <= i2c_idle;
                    end  

default:            begin
                    temperature<=13'b0;
                    end                                                    
endcase
end
end


assign tempout = temperature;
assign data = sda;
assign scl1=scl;

endmodule