Estoy programando un Spartan 3AN utilizando ISE y me gustaría implementar un código simple que use un Fifo:
Cuando presiono un botón, se envían datos al FIFO y cuando presiono otro botón, se lee el fifo y los datos se envían a los LED ...
Desafortunadamente, tengo un error que ocurre:
ERROR: HDLParsers: 3324 - "D: /.../ TOP_MODULE.vhd" Línea 129. Modo IN El dout formal de Led_out sin valor predeterminado debe estar asociado con un valor real.
Y no sé cómo cambiarlo ... Aquí está mi módulo superior y el componente Led_out:
MÓDULO SUPERIOR:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TOP_MODULE is
port (
M_CLK : IN STD_LOGIC;
BUTTON_T15 : IN STD_LOGIC;
BUTTON_T16 : IN STD_LOGIC;
LEDS : OUT STD_LOGIC_VECTOR (7 downto 0)
);
end TOP_MODULE;
architecture Behavioral of TOP_MODULE is
component Data_generator is
PORT (
M_CLK : IN STD_LOGIC;
BUTTON_T15 : IN STD_LOGIC;
wr_en : OUT STD_LOGIC;
full : IN STD_LOGIC;
DATA : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
end component;
component fifo_generator_v9_3 is
PORT (
M_CLK : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
end component;
signal RESET, WRITE_EN, READ_EN, FIFO_FULL, FIFO_EMPTY : STD_LOGIC;
signal DATA_IN, DATA_OUT : STD_LOGIC_VECTOR(17 downto 0)";
component Led_out is
PORT (
M_CLK : IN STD_LOGIC;
BUTTON_T16 : IN STD_LOGIC;
rd_en : OUT STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR (7 downto 0);
dout : IN STD_LOGIC_VECTOR(17 DOWNTO 0)
);
end component;
begin
U100:Data_generator
port map(
M_CLK,
BUTTON_T15,
WRITE_EN,
FIFO_FULL,
DATA_IN
);
U101:fifo_generator_v9_3
port map (
M_CLK,
RESET,
DATA_IN,
WRITE_EN,
READ_EN,
DATA_OUT,
FIFO_FULL,
FIFO_EMPTY
);
U102:Led_out
port map (
M_CLK,
BUTTON_T16,
READ_EN,
DATA_OUT
);
end Behavioral;
COMPONENTE LED_OUT:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Led_out is
Port (M_CLK : in STD_LOGIC;
BUTTON_T16 : IN STD_LOGIC;
rd_en : out STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR (7 downto 0);
dout : in STD_LOGIC_VECTOR (17 downto 0)
);
end Led_out;
architecture Behavioral of Led_out is
signal cnt : integer range 0 to 1:=0;
begin
process (M_CLK)
begin
if rising_edge (BUTTON_T16) then
rd_en <='1';
cnt <=1;
if cnt =1 then
LEDS <=dout (17 downto 10);
end if;
else
rd_en <='0';
end if;
end process;
end Behavioral;
Mi pregunta es: ¿Puede alguien explicar de dónde proviene este error y cómo cambiarlo?
Este es mi primer uso de FIFO en VHDL ...
Gracias de antemano!