FIFO: duda en proceso (clk)

library IEEE;  
use IEEE.STD_LOGIC_1164.ALL;  
use IEEE.STD_LOGIC_ARITH.ALL;  
--use IEEE.STD_LOGIC_UNSIGNED.ALL;  
use ieee.std_logic_signed.all;  

entity fifo is  
    port (  clk : in std_logic;  
          read_data : in   std_logic;                                       --enable read,should be '0' when not in use.  
          insert : in   std_logic;                                          --enable write,should be '0' when not in use.  
          delete : in std_logic;  
          datain : in std_logic_vector (7 downto   0);                      --input data  
          dataout : out std_logic_vector(7 downto   0);                 --output data           
          empty : out std_logic :=   '1';                                   --set   as '1' when the queue is empty  
          full : out std_logic  :=   '0';                                       --set as '1' when the queue is full  
          no_insert : out std_logic;  
          no_delete : out std_logic  
         );  
end fifo;  

architecture Behavioral of fifo is  
    type memory_type is array (0 to 255) of std_logic_vector(7 downto 0);  
    signal memory : memory_type :=(others => (others =>   '0'));            --memory for queue.  
    signal rp,wp,tmp_ptr : std_logic_vector(7 downto 0) :="00000000";       --read and write pointers.  
    signal isfull : std_logic := '0';  
    signal isempty : std_logic := '1';  
    begin  
        --dataout <= "00000000";  
        process(clk)  
        begin  
            -- Reading Process                     
                -- Read when not empty  
                -- empty when Write_ptr = Read_ptr  
                -- increment as 0 1 2....255 0 1 2....255  
                -- If Last_wrt is high set low Last_rd,  
                -- overwrite Last_rd as high if actually   reading take place  
            if(clk'event and clk='1' and read_data ='1')   then                         --read the tail of FIFO  
                --if(isempty = '1') then  
                --  dataout <= "00000000";  
                --else   
                    dataout <= memory(conv_integer(rp));  
                --end if;  
            end if;  
            if(clk'event and clk='1' and insert ='1')   then                                --insert on the   top/head of FIFO  
                --if(isfull = '1') then   
                    --no_insert <= '1 ;  
                    --dataout <= "00000000";  
                --else  
                    no_insert <= '0';  
                    memory(conv_integer(wp)) <= datain;  
                    dataout <= datain;  
                    --if(wp = "11111111") then  
                    --  wp <= "00000000";  
                    --else   
                    --  wp <= wp + 1;  
                    --end if;  
                --end if;  
                --if(wp = rp) then  
                --      full <= '1';  
                --      isfull <= '1';  
                --  else   
                --      full <= '0';  
                --      isfull <= '0';  
                --end if;  
            end if;  

            if(clk'event and clk='1' and delete ='1')   then                            --pop/delete the tail   of FIFO  
                --if(isempty = '1') then  
                --  no_delete <='1';  
                --  dataout <= "00000000";  
                --else   
                    no_delete <= '0';  
                    dataout <= memory(conv_integer(rp));  
                --  if(rp = "11111111") then  
                --      rp <= "00000000";  
                --  else   
                        rp <= rp + 1;  
                --  end if;  
                --  if(rp = wp) then  
                --      empty <= '1';  
                --      isempty <= '1';  
                --  else  
                --      empty <= '0';  
                --      isempty <= '0';  
                --  end if;  
                --end if;  
            end if;  
            if(rp = "11111111")   then                                          --resetting read pointer.  
                rp <= "00000000";  
            end if;  
            if(wp = "11111111")   then                                          --resetting read pointer.  
                wp <= "00000000";  
            end if;  

            if(wp = rp and insert = '1')   then                                         --checking whether queue is full or not  
                full <='1';               
            else  
                full <='0';  
            end if;  

            if(wp = rp and delete = '1')   then                                     --checking whether queue is empty or not  
                empty <='1';  
            else  
                empty <='0';  
            end if;       
        end process;  

end Behavioral;

En el código vhdl anterior para FIFO no estoy obteniendo la simulación de escritura de testbench. A pesar de que el búfer FIFO no está lleno, entonces también el lleno se vuelve igual a 1. ¿Puede alguien por favor ayudarme a solucionar el error?

cuando el proceso (clk) se ejecuta cada vez que se hace clic en clk tick, ¿qué ocurre exactamente ... se llaman todos los ifs simultáneamente? Me refiero a todas las funciones diferentes en el proceso (clk) que bloquea el ron al mismo tiempo en paralelo?