Este es el módulo superior que combina el registro de desplazamiento circular, el multiplexor y el sumador.
'timescale 1ns / 1ps
module top(
input CLK,
input [9:0] imgPixel,
output [15:0] WORD_OUT
);
integer j;
reg imgPixBit;
wire [15:0] word;
reg [3:0] counter;
wire select;
wire [15:0] reg_mx0 = 16'd0,reg_mx1= 16'd0,reg_mx2= 16'd0,reg_add0= 16'd0;
// Instantiate the Unit Under Test (UUT)
cir_shift_reg_v csr (
.CLK(CLK),
.WORD_OUT(word)
);
initial
begin
j=4'd0;
counter = 4'd0;
end
always @(posedge CLK)
begin
if (j<10)
begin
imgPixBit = imgPixel[j];
j = j + 1;
counter = counter + 1;
end
else
begin
j = 4'd0;
counter = 4'd0;
end
end
mux mx0 (
.CLK(CLK),
.WORD_IN1(word),
.WORD_IN2(16'd0),
.SELECT_BIT_IN(imgPixBit),
.WORD_OUT(reg_mx0)
);
control crtl0 (
.CLK(CLK),
.counter(counter),
.condition(4'd0),
.SELECT_BIT_OUT(select_mx1)
);
mux mx1 (
.CLK(CLK),
.WORD_IN1(reg_add0),
.WORD_IN2(16'd0),
.SELECT_BIT_IN(select_mx1),
.WORD_OUT(reg_mx1)
);
adder add0 (
.CLK(CLK),
.WORD_IN1(reg_mx0),
.WORD_IN2(reg_mx1),
.WORD_OUT(reg_add0)
);
control crtl1 (
.CLK(CLK),
.counter(counter),
.condition(4'd9),
.SELECT_BIT_OUT(select_mx2)
);
mux mx2 (
.CLK(CLK),
.WORD_IN1(reg_add0),
.WORD_IN2(reg_mx2),
.SELECT_BIT_IN(select_mx2),
.WORD_OUT(reg_mx2)
);
assign WORD_OUT = reg_mx2;
endmodule
Módulo de registro de desplazamiento circular
module cir_shift_reg_v(
input CLK,
output reg [15:0] WORD_OUT
);
parameter initialValue = {16'h0,16'h1,16'h2,16'h3,16'h4,16'h5,16'h6,16'h7,16'h8,16'h9};
//This works because concatenation makes it a 160bit wide value.
reg [15:0] wordShiftReg[9:0];
integer i;
initial begin
for (i=0;i<10;i=i+1)
begin
wordShiftReg[i] = initialValue[((9-i)*16)+:16];
end
end
always @(posedge CLK)
begin
WORD_OUT <= wordShiftReg[0];
for (i=0;i<9;i=i+1) begin
wordShiftReg[i] <= wordShiftReg[i+1];
end
wordShiftReg[9] <= WORD_OUT;
end
endmodule
Módulo Mux
'timescale 1ns / 1ps
module mux(
input CLK,
input [15:0] WORD_IN1,
input [15:0] WORD_IN2,
input SELECT_BIT_IN,
output reg [15:0] WORD_OUT
);
always @(posedge CLK)
WORD_OUT = (SELECT_BIT_IN) ? WORD_IN1 : WORD_IN2;
endmodule
Módulo de control
'timescale 1ns / 1ps
module control(
input CLK,
input [3:0] counter,
input [3:0] condition,
output reg SELECT_BIT_OUT
);
always @(posedge CLK)
SELECT_BIT_OUT = (counter==condition) ? 1 : 0;
endmodule
Módulo Adder
'timescale 1ns / 1ps
module adder(
input CLK,
input [15:0] WORD_IN1,
input [15:0] WORD_IN2,
output reg [15:0] WORD_OUT
);
always @(posedge CLK)
WORD_OUT = WORD_IN1 + WORD_IN2;
endmodule
El registro de desplazamiento circular funciona perfectamente, pero no estoy seguro de los otros módulos.
El error se muestra con reg_mx0, reg_mx1 durante la instanciación del módulo Adder.
¿Puede alguien ayudarme por favor? Cualquier optimización en el código es bienvenida.