Tengo un módulo simple que divide filas entre diferentes motores. En este módulo, row_start_r es un registro que es un contador que omite la cuenta por un desplazamiento específico y, finalmente, se escribe en un FIFO. El siguiente código funciona en simulación, pero no en el FPGA real.
Lo único sospechoso en el informe de síntesis es que la herramienta establece los bits inferiores del registro row_start_r en 0 y da la siguiente advertencia
INFO: propagating constant 0 across sequential element (i_13/\LOAD_BALANCER/row_start_reg_reg[0]
INFO: propagating constant 0 across sequential element (i_13/\LOAD_BALANCER/row_start_reg_reg[1] )
INFO: propagating constant 0 across sequential element(i_13/\LOAD_BALANCER/row_start_reg_reg[2] )
El siguiente es mi código.
'timescale 1 ns / 1 ps
module split_rows #(
parameter NUM_ENGINES = 2
)(
input wire clk,
input wire rst,
output wire done,
input wire [63:0] num_rows,
output wire ready_out,
input wire [NUM_ENGINES-1:0] engine_ready_in,
output [63:0] start_row_pos_out,
output [63:0] end_row_pos_out,
output [NUM_ENGINES-1:0] engine_select_wr_out
);
reg [2:0] engine_id; /// num_engines
wire fifo_empty_s;
wire fifo_full_s;
reg fifo_rd_en;
wire fifo_wr_en;
reg [NUM_ENGINES-1:0] engine_select_s;
reg [63:0] row_start_r;
wire [63:0] row_start_out;
reg [63:0] start_row_pos_out_s;
wire [63:0] end_row_pos_out_s;
always @(posedge clk)
begin
if (rst == 1'd1) engine_id <= 3'd0;
else if (engine_id == NUM_ENGINES-1) engine_id <= 3'd0;
else engine_id <= engine_id + 3'd1;
end
always @(posedge clk)
begin
if(rst) begin
row_start_r <= 64'd0;
end
else if (fifo_wr_en) begin
row_start_r <= row_start_r + 64'd32; //skip_offset ;
end
end
assign fifo_wr_en = !rst && !fifo_full_s && (row_start_r < num_rows);
fifo #(.DEPTH(64), .WIDTH(64), .AFULLCNT(60), .RAM_STYLE("block") ) offset_holder (
.clk (clk),
.reset (rst),
.push (fifo_wr_en),
.din (row_start_r),
.afull (fifo_full_s),
.full (),
.cnt (),
.oclk (clk),
.pop (fifo_rd_en), // from write engine
.dout (row_start_out),
.empty (fifo_empty_s),
.rcnt ()
);
always @(*)
begin
engine_select_s = 0;
fifo_rd_en = 0;
start_row_pos_out_s = 64'd0;
if ( !rst && engine_ready_in[engine_id] == 1 && !fifo_empty_s )
begin
engine_select_s[engine_id] = 1;
fifo_rd_en = 1;
start_row_pos_out_s = row_start_out;
end
end
assign end_row_pos_out_s = (start_row_pos_out_s + 64'd32 >= num_rows) ? num_rows: row_start_out + 64'd32;
assign ready_out = !rst && !fifo_empty_s;
assign start_row_pos_out = start_row_pos_out_s;
assign end_row_pos_out = end_row_pos_out_s ;
assign engine_select_wr_out = engine_select_s ;
done_stall #(
.LENGTH (4)
) DONE_OUT (
.clk (clk),
.rst (rst),
.done_in (fifo_empty_s),
.done_out (done)
);
endmodule
Si alguien puede revisarlo y señalar el error que sería realmente útil. Gracias.