Estoy intentando crear un módulo con VHDL para mi DE2 donde lo fácil ("Hola mundo") es casi imposible. El fundamento es que estoy tratando de ejecutar Hello World:
Y ahora estoy siguiendo la instrucción que no funciona con mi versión de Quartus II v13:
¿Quésignificaelmensajedeerror?¿Estoyhaciendoalgoincorrectoporloquesepuedeverenlascapturasdepantalla?
Info:*******************************************************************Info:RunningQuartusII32-bitGenerateHDLInterfaceInfo:Version13.0.1Build23206/12/2013ServicePack1SJWebEditionInfo:Copyright(C)1991-2013AlteraCorporation.Allrightsreserved.Info:YouruseofAlteraCorporation'sdesigntools,logicfunctionsInfo:andothersoftwareandtools,anditsAMPPpartnerlogicInfo:functions,andanyoutputfilesfromanyoftheforegoingInfo:(includingdeviceprogrammingorsimulationfiles),andanyInfo:associateddocumentationorinformationareexpresslysubjectInfo:tothetermsandconditionsoftheAlteraProgramLicenseInfo:SubscriptionAgreement,AlteraMegaCoreFunctionLicenseInfo:Agreement,orotherapplicablelicenseagreement,including,Info:withoutlimitation,thatyouruseisforthesolepurposeofInfo:programminglogicdevicesmanufacturedbyAlteraandsoldbyInfo:Alteraoritsauthorizeddistributors.PleaserefertotheInfo:applicableagreementforfurtherdetails.Info:Processingstarted:FriAug1609:52:042013Info:Command:quartus_mapnot_a_project--generate_hdl_interface=C:/Users/student/Desktop/KTH/colombia/de2_sram_controller.vhd--source=C:/Users/student/Desktop/KTH/colombia/de2_sram_controller.vhd--set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/student/AppData/Local/Temp/alt5933_4160154550827554259.dir/0002_sopcqmap/--ini=disable_check_quartus_compatibility_qsys_only=onError:VHDLsyntaxerroratde2_sram_controller.vhd(20)neartext€File:/users/student/desktop/kth/colombia/de2_sram_controller.vhdLine:20Error:VHDLsyntaxerroratde2_sram_controller.vhd(20)neartext"€"; expecting ";" File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 20
Error: VHDL syntax error at de2_sram_controller.vhd(20) near text ™ File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 20
Error: VHDL syntax error at de2_sram_controller.vhd(21) near text € File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 21
Error: VHDL syntax error at de2_sram_controller.vhd(21) near text ™ File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 21
Warning: Quartus II 32-bit Generate HDL Interface was unsuccessful. 5 errors, 0 warnings
Error: Peak virtual memory: 364 megabytes
Error: Processing ended: Fri Aug 16 09:52:06 2013
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:01
Error: No modules found when analyzing null.
Actualizar
El error de compilación de mi VHDL es ahora
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Aug 16 17:48:44 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab3 -c lab3
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10500): VHDL syntax error at lab3.vhd(20) near text
Error (10500): VHDL syntax error at lab3.vhd(20) near text ""; expecting ";"
Error (10500): VHDL syntax error at lab3.vhd(20) near text
Error (10500): VHDL syntax error at lab3.vhd(21) near text
Error (10500): VHDL syntax error at lab3.vhd(21) near text
Info (12021): Found 0 design units, including 0 entities, in source file lab3.vhd
Error (10430): VHDL Primary Unit Declaration error at de2_sram_controller.vhd(3): primary unit "de2_sram_controller" already exists in library "work"
Error (10784): HDL error at lab3.vhd(3): see declaration for object "de2_sram_controller"
Error (10500): VHDL syntax error at de2_sram_controller.vhd(22) near text
Error (10500): VHDL syntax error at de2_sram_controller.vhd(22) near text ""; expecting ";"
Error (10500): VHDL syntax error at de2_sram_controller.vhd(22) near text
Error (10500): VHDL syntax error at de2_sram_controller.vhd(23) near text
Error (10500): VHDL syntax error at de2_sram_controller.vhd(23) near text
Info (12021): Found 0 design units, including 0 entities, in source file de2_sram_controller.vhd
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 12 errors, 1 warning
Error: Peak virtual memory: 476 megabytes
Error: Processing ended: Fri Aug 16 17:48:45 2013
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 14 errors, 1 warning
El código es
library ieee;
use ieee.std_logic_1164.all;
entity de2_sram_controller is
port (
signal chipselect : in std_logic;
signal write, read : in std_logic;
signal address : in std_logic_vector(17 downto 0);
signal readdata : out std_logic_vector(15 downto 0);
signal writedata : in std_logic_vector(15 downto 0);
signal byteenable : in std_logic_vector(1 downto 0);
signal SRAM_DQ : inout std_logic_vector(15 downto 0);
signal SRAM_ADDR : out std_logic_vector(17 downto 0);
signal SRAM_UB_N, SRAM_LB_N : out std_logic;
signal SRAM_WE_N, SRAM_CE_N : out std_logic;
signal SRAM_OE_N : out std_logic
);
end de2_sram_controller;
architecture dp of de2_sram_controller is
begin
SRAM_DQ <= writedata when write = ’1’
else (others => ’Z’);
readdata <= SRAM_DQ;
SRAM_ADDR <= address;
SRAM_UB_N <= not byteenable(1);
SRAM_LB_N <= not byteenable(0);
SRAM_WE_N <= not write;
SRAM_CE_N <= not chipselect;
SRAM_OE_N <= not read;
end dp;