Estoy utilizando el software Vivado 2016.2 y el tablero Basys3 para crear un instrumento musical básico. He producido las notas do (SW1), re (SW2), mi (SW3), fa (SW4), entonces (SW5), la (SW6), ti (SW7) y cada una de ellas se escucha cuando se gira un interruptor. en. Quiero poder producir un acorde o melodía o notas que contengan un intervalo de tiempo entre sí (no solo una nota) cuando enciendo SW8. Por ejemplo, quiero una simple canción de feliz cumpleaños para jugar. ¿Cómo hago eso?
Aquí están los códigos para producir diferentes ondas de frecuencia para cada nota:
module Clk_Notes(
input CLK,
output reg clk_do,
output reg clk_re,
output reg clk_mi,
output reg clk_fa,
output reg clk_so,
output reg clk_la,
output reg clk_ti,
output reg clk_fast_cs
);
reg [17:0] count_do = 0;
reg [17:0] count_re = 0;
reg [17:0] count_mi = 0;
reg [17:0] count_fa = 0;
reg [17:0] count_so = 0;
reg [17:0] count_la = 0;
reg [17:0] count_ti = 0;
reg [22:0] count_fast_cs = 0;
initial begin
clk_do = 0;
clk_re = 0;
clk_mi = 0;
clk_fa = 0;
clk_so = 0;
clk_la = 0;
clk_ti = 0;
end
always @ (posedge CLK) begin
count_do <= (count_do == 191112)? 0 : count_do + 1;
clk_do <= (count_do == 0)? ~clk_do : clk_do;
count_re <= (count_re == 170261)? 0 : count_re + 1;
clk_re <= (count_re == 0)? ~clk_re : clk_re;
count_mi <= (count_mi == 151685)? 0 : count_mi + 1;
clk_mi <= (count_mi == 0)? ~clk_mi : clk_mi;
count_fa <= (count_fa == 143172)? 0 : count_fa + 1;
clk_fa <= (count_fa == 0)? ~clk_fa : clk_fa;
count_so <= (count_so == 127552)? 0 : count_so + 1;
clk_so <= (count_so == 0)? ~clk_so : clk_so;
count_la <= (count_la == 113635)? 0 : count_la + 1;
clk_la <= (count_la == 0)? ~clk_la : clk_la;
count_ti <= (count_ti == 101238)? 0 : count_ti + 1;
clk_ti <= (count_ti == 0)? ~clk_ti : clk_ti;
count_fast_cs <= (count_fast_cs == 417)? 0 : count_fast_cs + 1;
clk_fast_cs <= (count_fast_cs == 0)? ~clk_fast_cs : clk_fast_cs;
end
endmodule
Aquí están los códigos para asignar cada nota a cada interruptor:
module Instrument_StudentB(
input CLK,
input SW1, SW2, SW3, SW4, SW5, SW6, SW7, CS_20,
output reg [11:0] Music
);
wire clk_do, clk_re, clk_mi, clk_fa, clk_so, clk_la, clk_ti, clk_do, clk_fast_cs, Notes;
reg [11:0] speaker_out;
Clk_Notes notes (CLK, clk_do, clk_re, clk_mi, clk_fa, clk_so, clk_la, clk_ti, clk_fast_cs);
assign Notes = (SW1)? clk_do:
(SW2)? clk_re:
(SW3)? clk_mi:
(SW4)? clk_fa:
(SW5)? clk_so:
(SW6)? clk_la:
(SW7)? clk_ti:0;
always @ (posedge clk_fast_cs) begin
speaker_out <= speaker_out << 1 | Notes;
end
always @ (posedge CS_20) begin
Music <= speaker_out;
end
//assign speaker_out[11] = Music;
endmodule