no puede enviar caracteres usando fpga cyclone iv

Estoy tratando de conectar mi FPGA Cylone IV (CoreEP4CE6) con Raspberry Pi 3 para la comunicación a través de UART. El proceso (uart_rx) para recibir datos funciona bien, sin embargo, cuando coloco otro proceso (uart_tx) para transmitir datos, ambos procesos fallan. No sé por qué, en la simulación todo funciona bien. ¿Puedo conectar Raspberry pins tx y rx directamente a FPGA in / out pins?

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity uart is
generic(
    freq: integer := 433 -- 50000000/115200
);

port(
    rx: in std_logic;
    tx: out std_logic := '1';
    data: out std_logic_vector(7 downto 0);     
    clk: in std_logic
);
end uart;

architecture uart_arch of uart is
begin
-- uart rx process
-- receive bytes through rx port
uart_rx: process(rx, clk)
    variable start_recv: bit := '0';
    variable timeout: integer := 0;
    variable count: integer := 0;
begin
    if rising_edge(clk) then
        if rx = '0' and start_recv = '0' then
            start_recv := '1';
            count := 0;
            timeout := 0;
        elsif start_recv = '1' then
            if count >= freq then
                count := 0;
                timeout := timeout + 1;
                if timeout <= 8 then
                    data(timeout-1) <= rx;
                elsif rx = '1' then -- wait for idle
                    timeout := 0;
                    start_recv := '0';
                end if;
            end if;
            count := count + 1;
        end if;
    end if;
end process;

uart_tx: process(clk)
    variable start_send: bit := '0';
    variable timeout: integer := 0;
    variable count: integer := 0;

    constant message: string(1 to 5) := "hello";
    variable buff: std_logic_vector(7 downto 0);
    variable p: integer := 1;
begin
    if rising_edge(clk) then
        if start_send = '0' and count >= freq then
            if p > message'Length then
                p := 1;
            end if;

            tx <= '0';
            buff := std_logic_vector(
                        to_unsigned(character'pos(message(p)), 8)); 
            start_send := '1';

            count := 0;
            timeout := 0;
        elsif start_send = '1' then
            if count >= freq then
                count := 0;
                timeout := timeout + 1;
                if timeout <= 8 then
                    tx <= buff(timeout-1);
                else
                    tx <= '1'; -- put in idle
                    p := p + 1; -- next char

                    timeout := 0;
                    start_send := '0';
                end if;
            end if;
        end if;
        count := count + 1;
    end if;
end process;
end uart_arch;