Verilog No se pueden resolver varios controladores constantes para la red

He buscado esto en google pero las respuestas no son claras para mí. Actúa como si fuera muy estúpido, por favor, ya que soy un estudiante de primer año de ECE. Mi laboratorio quiere que use Verilog para programar un DE0 para mostrar los números 0-9 en sus pantallas dependiendo de los interruptores que giramos. Tuvimos la tarea de programarlo en los estilos de comportamiento, flujo de datos y estructural. He compilado y programado con éxito la placa en el estilo de comportamiento y flujo de datos. Mi lucha es con lo estructural. Recibo los siguientes errores en la compilación.

Error (10028): Can't resolve multiple constant drivers for net "W_OR_NOT_X_OR_NOT_Y_OR_NOT_Z" at Lab_3_b_structural.v(181)

Error (10028): Can't resolve multiple constant drivers for net 
"W_OR_X_OR_Y_OR_NOT_Z" at Lab_3_b_structural.v(176)

Error (10029): Constant driver at Lab_3_b_structural.v(142)

Error (10029): Constant driver at Lab_3_b_structural.v(157)

Error (12152): Can't elaborate user hierarchy "structural:h0"

Error (293001): Quartus II Full Compilation was unsuccessful. 7 errors, 10 warnings

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 5 errors, 10 warnings

Error: Peak virtual memory: 453 megabytes
Error: Processing ended: Sat Oct 08 17:13:54 2016
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00
Error: Peak virtual memory: 453 megabytes
Error: Processing ended: Sat Oct 08 17:13:54 2016
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00

/* In this lab we are using Verilog to create the seven segment display on the DE0. 
We had to perform the lab using behavioral, dataflow, and structural. So, three tests */

module Lab_3_b_structural(SW, HEX0, HEX1, HEX2);

    input [9:0] SW;

    output [6:0] HEX0, HEX1, HEX2;

    wire [6:0] hex0, hex1, hex2;
    //DE0 is common anode
    assign HEX0 = ~hex0;
    assign HEX1 = ~hex1;
    assign HEX2 = ~hex2;

    structural h0 (SW[3:0], hex0);
    structural h1 (SW[7:4], hex1);
    structural h2 ({2'b00,SW[9:8]}, hex2);
endmodule 

module structural (bcd, hex);

    input [3:0] bcd; //WXYZ

    output [6:0] hex; //ABCDEFG

    wire W,X,Y,Z;
    assign W = bcd[3];
    assign X = bcd[2];
    assign Y = bcd[1];
    assign Z = bcd[0];

    //NOTS (Used By all Segments)
    wire W_NOT;
    wire X_NOT;
    wire Y_NOT;
    wire Z_NOT;
    not not1 (W_NOT, W);
    not not2 (X_NOT, X);
    not not3 (Y_NOT, Y);
    not not4 (Z_NOT, Z);


    //A =(W|X|Y|~Z)&(W|~X|Y|Z)
    wire W_OR_X_OR_Y_NOT_Z; 
    wire W_OR_NOT_X_OR_Y_OR_Z;

    or or1A (W_OR_X_OR_Y_NOT_Z, 
    W,
    X,
    Y,
    Z_NOT);
    or or2A (W_OR_NOT_X_OR_Y_OR_Z, 
    W, 
    NOT_X,
    Y, 
    Z);
    and FinalA (hex[0], 
    W_OR_NOT_X_OR_Y_OR_Z, 
    W_OR_X_OR_Y_NOT_Z);

    //B = (W|~X|Y|~Z)&(W|~X|~Y|Z)
    wire W_OR_NOT_X_OR_Y_OR_NOT_Z;
    wire W_OR_NOT_X_OR_NOT_Y_OR_Z;

    or or1B (W_OR_NOT_X_OR_Y_OR_NOT_Z, 
    W, 
    NOT_X,
    Y, 
    NOT_Z);
    or or2B (W_OR_NOT_X_OR_NOT_Y_OR_Z, 
    W,
    NOT_X,
    NOT_Y,
    Z);
    and FinalB (hex[1],
    W_OR_NOT_X_OR_Y_OR_NOT_Z,
    W_OR_NOT_X_OR_NOT_Y_OR_Z);

    //C = (W|X|~Y|Z)
    wire W_OR_X_OR_NOT_Y_OR_Z;

    or FinalC (hex[2], W_OR_X_OR_NOT_Y_OR_Z);

    //D = (~X&Y)|(~X&~Z)|(X&~Y&Z)|(Y&~Z)|W
    wire NOT_X_AND_Y;
    wire NOT_X_AND_NOT_Z;
    wire X_AND_NOT_Y_AND_Z;

    and and1D (NOT_X_AND_Y, 
    NOT_X, 
    Y);
    and and2D (NOT_X_AND_NOT_Z,
    NOT_X, 
    NOT_Z);
    and and3D (X_AND_NOT_Y_AND_Z,
    X,
    NOT_Y,
    Z);
    or finalD (hex[3], 
    NOT_X_AND_Y, 
    NOT_X_AND_NOT_Z, 
    X_AND_NOT_Y_AND_Z,
    W);

    //E = (~W&~X&~Y&~Z)|~W&~X&Y&~Z)|(~W&X&Y&~Z)|(W&~X&~Y&~Z)
    wire NOT_W_AND_NOT_X_AND_NOT_Y_AND_NOT_Z;
    wire NOT_W_AND_NOT_X_AND_Y_AND_NOT_Z;
    wire NOT_W_AND_X_AND_Y_AND_NOT_Z;
    wire W_AND_NOT_X_AND_NOT_Y_AND_NOT_Z;

    and and1E (NOT_W_AND_NOT_X_AND_NOT_Y_AND_NOT_Z, 
    NOT_W,
    NOT_X, 
    NOT_Y,
    NOT_Z);
    and and2E (NOT_W_AND_NOT_X_AND_Y_AND_NOT_Z,
    NOT_W,
    NOT_X,
    Y, 
    NOT_Z);
    and and3E (NOT_W_AND_X_AND_Y_AND_NOT_Z, 
    NOT_W,
    X, 
    Y, 
    NOT_Z);
    and and4E (W_AND_NOT_X_AND_NOT_Y_AND_NOT_Z, 
    W, 
    NOT_X,
    NOT_Y,
    NOT_Z);
    or finalE (hex[4], 
    NOT_W_AND_NOT_X_AND_NOT_Y_AND_NOT_Z,
    NOT_W_AND_NOT_X_AND_Y_AND_NOT_Z,
    NOT_W_AND_X_AND_Y_AND_NOT_Z,
    W_AND_NOT_X_AND_NOT_Y_AND_NOT_Z);

    //F = (W|X|Y|~Z)&(W|X|~Y|Z)&(W|X|~Y|~Z)&(W|~X|~Y|~Z)
    wire W_OR_X_OR_Y_OR_NOT_Z;
    wire W_OR_X_OR_NOT_Y_OR_NOT_Z;
    wire W_OR_NOT_X_OR_NOT_Y_OR_NOT_Z;

    or or1F (W_OR_X_OR_Y_OR_NOT_Z, 
    W, 
    X, 
    Y,
    NOT_Z);
    or or2F (W_OR_X_OR_NOT_Y_OR_Z, 
    W, 
    X, 
    NOT_Y,
    Z);
    or or3F (W_OR_X_OR_NOT_Y_OR_NOT_Z, 
    W, 
    X, 
    NOT_Y,
    NOT_Z);
    or or4F (W_OR_NOT_X_OR_NOT_Y_OR_NOT_Z, 
    W, 
    NOT_X,
    NOT_Y,
    NOT_Z);
    and finalF (hex[5],
    W_OR_X_OR_Y_OR_NOT_Z,
    W_OR_X_OR_NOT_Y_OR_Z,
    W_OR_X_OR_NOT_Y_OR_NOT_Z,
    W_OR_NOT_X_OR_NOT_Y_OR_NOT_Z);

    //G = (W|X|Y|Z)&(W|X|Y|~Z)&(W|~X|~Y|~Z)
    wire W_OR_X_OR_Y_OR_Z;

    or or1G (W_OR_X_OR_Y_OR_Z,
    W, 
    X,
    Y, 
    Z);
    or or2G (W_OR_X_OR_Y_OR_NOT_Z,
    W,
    X,
    Y,
    NOT_Z);
    or or3G (W_OR_NOT_X_OR_NOT_Y_OR_NOT_Z,
    W, 
    NOT_X, 
    NOT_Y,
    NOT_Z);
    and finalG (hex[6],
    W_OR_X_OR_Y_OR_Z,
    W_OR_X_OR_Y_OR_NOT_Z,
    W_OR_NOT_X_OR_NOT_Y_OR_NOT_Z);
endmodule