Estoy haciendo un ADC (en VHDL) para Spartan-3AN. Desafortunadamente, tengo que programar mi FPGA (programa FPGA solamente) un tiempo aleatorio antes del amplificador de ganancia programable ( Spartan 3AN User Guide página 73) funciona correctamente ... Y cuando programo el flash, nunca funciona correctamente ... Pongo mi código al final de este tema para que pueda verlo, pero mi pregunta es:
¿Alguien sabe el tipo de problemas que pueden hacerme tener que programar tiempos aleatorios en mi FPGA para obtener el código correcto?
Aquí está mi código:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adc_dac is
Port ( CLK_50MHZ : in STD_LOGIC;
SPI_MOSI : out STD_LOGIC;
AMP_CS : out STD_LOGIC :='1';
SPI_SCK : out STD_LOGIC :='0';
AMP_SHDN : out STD_LOGIC :='0';
AD_CONV : out STD_LOGIC;
ADC_OUT : in STD_LOGIC;
led : out STD_LOGIC_vector (7 downto 0)
);
end adc_dac;
architecture Behavioral of adc_dac is
type state_type is ( pga_load,
idle, sendBitPGA, clockHighPGA,
catchADC, setADC
);
signal state : state_type:=pga_load;
-- Extra counter
signal cnt : integer range 0 to 34 := 8;
signal cnt_SCK : integer range 0 to 1 := 0;
-- Programmable Gain Amplifier
signal pga_data : std_logic_vector (7 downto 0) := "00010001";
signal counter_10MHZ: integer range 0 to 10 := 0;
-- Auxiliary signals ADC
signal Data : std_logic_vector (13 downto 0);
signal ADC_path: std_logic:='0';
signal output : std_logic_vector (13 downto 0) := "10000000000000";
begin
--**********************************
--** STATE MACHINE **
--**********************************
process (CLK_50MHZ)
begin
if (rising_edge(CLK_50MHZ)) then
case state is
when idle =>
if ADC_path = '1' then
ADC_path <= '0';
AD_CONV <= '0';
cnt <= 34;
state <= setADC;
else
SPI_SCK <= '0';
AD_CONV <= '1';
ADC_path <= '1';
state <= idle;
end if;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--^^ PGA interface ^^
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
when pga_load =>
SPI_SCK <= '0';
cnt <= 8;
AMP_SHDN <= '0';
pga_data <= "00010001";
AMP_CS <= '0';
state <= sendBitPGA;
when sendBitPGA =>
if (counter_10MHZ = 5) then
if (cnt_SCK = 0) then
SPI_SCK <= '1';
cnt_SCK <= 1;
SPI_MOSI <= pga_data(7);
cnt <= cnt-1;
state <= clockHighPGA;
elsif(cnt_SCK = 1) then
SPI_SCK <= '0';
cnt_SCK <= 0;
end if;
if (cnt = 0) then
AMP_CS <= '1';
state <= idle;
end if;
counter_10MHZ <= 0;
else
counter_10MHZ <= counter_10MHZ + 1;
state <= sendBitPGA;
end if;
when clockHighPGA =>
pga_data <= pga_data(6 downto 0) & '0';
state <= sendBitPGA;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--^^ ADC interface ^^
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
when setADC =>
if (cnt = 0) then
AD_CONV <= '1';
output <= Data (13 downto 0);
led <= output (13 downto 6);
ADC_path <= '1';
state <= idle;
else
SPI_SCK <= '1';
cnt <= cnt-1;
state <= catchADC;
end if;
when catchADC =>
SPI_SCK <= '0';
if (cnt >= 18 and cnt <= 31) then
Data <= Data(12 downto 0) & ADC_OUT ;
end if;
state <= setADC;
end case;
end if;
end process;
end Behavioral;
Gracias de antemano!