Estoy trabajando en una implementación simple de neuronas en un kit de inicio de Xilinx Spartan-3E y obtengo la advertencia del tema. ¿Alguien me puede explicar por qué estoy recibiendo este error?
Mi código:
module NeuronMdl #(parameter NUMBER_OF_INPUTS= 2) (
input wire[NUMBER_OF_INPUTS:1] x, // Number of input bits.
output reg y // Output.
);
reg signed[7:0] w[NUMBER_OF_INPUTS:0]; // Weights array, w[0] is bias so there's no input as x[0].
reg signed[7:0] yTemp;
initial begin // Initial values for an OR Gate.
w[0]= 8'h00;
w[1]= 8'h01;
w[2]= 8'h01;
end // initial
always @(x) begin // Everytime there's a change in the input.
yTemp= w[0]+ w[1]* x[1]+ w[2]* x[2]; // Need to find a way to generate this for varying input bits.
y<= (yTemp> 0)? 1: 0; // Output only 1 or 0.
end // always
endmodule
archivo UCF:
# slide switches
NET "x<1>" LOC="L13" | PULLUP;
NET "x<2>" LOC="L14" | PULLUP;
# leds
NET "y" LOC="F12"; # led 0
Y las advertencias que estoy recibiendo:
WARNING:PhysDesignRules:367 - The signal <x<1>_IBUF> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <x<2>_IBUF> is incomplete. The signal does not drive any load pins in the design.
WARNING:Par:288 - The signal x<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal x<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.