He generado una RAM de puerto único (primitiva DP8KC) desde IP express usando la herramienta Lattice y luego estoy creando una instancia con el registro de desplazamiento de 48 bits, que está en el lado de entrada. La salida del registro de desplazamiento está conectada al lado del émbolo para guardar los datos de escritura del registro de desplazamiento. Luego, desde la memoria RAM, tengo que sacar datos en la placa mach x02. Pero estoy recibiendo un error al sintetizar en la herramienta de celosía.
.ERROR-@E: Net "sout[0]" in work.grayscale(verilog) has conflicting drivers, the connections are
@E: BN314 :"d:\led_project\program\tlc\sim\tlc\source\tlc.v":1:7:1:15|Net "sout[0]" in work.grayscale(verilog) has multiple drivers
también ayúdame, ¿puedo conectar directamente la salida del ram con la placa y cómo conectarlo? ¿Debo crear una instancia del ram con un diseño u otro módulo? ¿Es una buena práctica leer, escribir datos de 48 bits en 1 fila y luego leer, es decir, mostrar el led a bordo? Por favor sugiéreme con el código correcto.
Diseño de registro de desplazamiento (código Verilog)
module grayscale(s_in,gsclk,dcsel,xlat,blank,lod,tef,cs,sout,ch_out,sclk,xerr);
input s_in,gsclk,dcsel,xlat,blank,lod,tef,sclk;
input [1:0] cs;
output xerr;
output [47:0]sout;
output [15:0] ch_out;
reg [5:0] counter_q;
reg [47:0] temp;
wire [1:0] cs;
/*constant declarations for chip select */
'define cs1 2'b00
'define cs2 2'b01
'define cs3 2'b10
assign xerr = (lod |tef) ? 1'b0 :
1'b1;
assign gs_enable = (~dcsel& sclk==1'b1) ? 1'b1:
1'b0;
assign gs_int_cnt = (~blank & gsclk==1'b1) ? 1'b1:
1'b0;
assign ch_out = ('cs1==cs) ? temp[15:0]: (('cs2==cs) ? temp[31:16] : temp[47:32]);
/* assign ch_out = ('cs1==cs) ? sout[15:0]:
('cs2==cs) ? sout[16:31]: sout[32:47];*/
/* parameterized module instance */
shift_ram grayscale (.Clock(gsclk ), .ClockEn(1'b1 ), .Reset(1'b0 ), .WE(1'b1 ), .Address(2'b00 ),
.Data(s_in ), .Q(sout ));
always@( posedge gsclk)
begin
if(gs_enable==1'b1)
temp <= {temp[46:0],s_in};
else
temp <= 47'b0;
end
assign sout = temp;
always@(posedge gsclk)
begin
if(blank==1'b0)
counter_q <= counter_q + 1'b1;
else
counter_q <= 6'b0;
end
endmodule
Código RAM generado desde IP express
/* Verilog netlist generated by SCUBA Diamond_2.0_Production (151) */
/* Module Version: 7.1 */
/* C:\lscc\diamond.0\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 1000 -addr_width 2 -data_width 48 -num_rows 4 -cascade -1 -mem_init0 -writemode NORMAL -e */
/* Wed Jan 02 21:24:28 2013 */
'timescale 1 ns / 1 ps
module shift_ram (Clock, ClockEn, Reset, WE, Address, Data, Q);
input wire Clock;
input wire ClockEn;
input wire Reset;
input wire WE;
input wire [1:0] Address;
input wire [47:0] Data;
output wire [47:0] Q;
wire scuba_vhi;
wire scuba_vlo;
defparam shift_ram_0_0_2.INIT_DATA = "STATIC" ;
defparam shift_ram_0_0_2.ASYNC_RESET_RELEASE = "SYNC" ;
defparam shift_ram_0_0_2.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_0_2.CSDECODE_B = "0b000" ;
defparam shift_ram_0_0_2.CSDECODE_A = "0b000" ;
defparam shift_ram_0_0_2.WRITEMODE_B = "NORMAL" ;
defparam shift_ram_0_0_2.WRITEMODE_A = "NORMAL" ;
defparam shift_ram_0_0_2.GSR = "ENABLED" ;
defparam shift_ram_0_0_2.RESETMODE = "ASYNC" ;
defparam shift_ram_0_0_2.REGMODE_B = "NOREG" ;
defparam shift_ram_0_0_2.REGMODE_A = "NOREG" ;
defparam shift_ram_0_0_2.DATA_WIDTH_B = 9 ;
defparam shift_ram_0_0_2.DATA_WIDTH_A = 9 ;
DP8KC shift_ram_0_0_2 (.DIA8(Data[8]), .DIA7(Data[7]), .DIA6(Data[6]),
.DIA5(Data[5]), .DIA4(Data[4]), .DIA3(Data[3]), .DIA2(Data[2]),
.DIA1(Data[1]), .DIA0(Data[0]), .ADA12(scuba_vlo), .ADA11(scuba_vlo),
.ADA10(scuba_vlo), .ADA9(scuba_vlo), .ADA8(scuba_vlo), .ADA7(scuba_vlo),
.ADA6(scuba_vlo), .ADA5(scuba_vlo), .ADA4(Address[1]), .ADA3(Address[0]),
.ADA2(scuba_vlo), .ADA1(scuba_vlo), .ADA0(scuba_vhi), .CEA(ClockEn),
.OCEA(ClockEn), .CLKA(Clock), .WEA(WE), .CSA2(scuba_vlo), .CSA1(scuba_vlo),
.CSA0(scuba_vlo), .RSTA(Reset), .DIB8(Data[17]), .DIB7(Data[16]),
.DIB6(Data[15]), .DIB5(Data[14]), .DIB4(Data[13]), .DIB3(Data[12]),
.DIB2(Data[11]), .DIB1(Data[10]), .DIB0(Data[9]), .ADB12(scuba_vhi),
.ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo), .ADB8(scuba_vlo),
.ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo), .ADB4(Address[1]),
.ADB3(Address[0]), .ADB2(scuba_vlo), .ADB1(scuba_vlo), .ADB0(scuba_vhi),
.CEB(ClockEn), .OCEB(ClockEn), .CLKB(Clock), .WEB(WE), .CSB2(scuba_vlo),
.CSB1(scuba_vlo), .CSB0(scuba_vlo), .RSTB(Reset), .DOA8(Q[8]), .DOA7(Q[7]),
.DOA6(Q[6]), .DOA5(Q[5]), .DOA4(Q[4]), .DOA3(Q[3]), .DOA2(Q[2]),
.DOA1(Q[1]), .DOA0(Q[0]), .DOB8(Q[17]), .DOB7(Q[16]), .DOB6(Q[15]),
.DOB5(Q[14]), .DOB4(Q[13]), .DOB3(Q[12]), .DOB2(Q[11]), .DOB1(Q[10]),
.DOB0(Q[9]))
/* synthesis MEM_LPC_FILE="shift_ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam shift_ram_0_1_1.INIT_DATA = "STATIC" ;
defparam shift_ram_0_1_1.ASYNC_RESET_RELEASE = "SYNC" ;
defparam shift_ram_0_1_1.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_1_1.CSDECODE_B = "0b000" ;
defparam shift_ram_0_1_1.CSDECODE_A = "0b000" ;
defparam shift_ram_0_1_1.WRITEMODE_B = "NORMAL" ;
defparam shift_ram_0_1_1.WRITEMODE_A = "NORMAL" ;
defparam shift_ram_0_1_1.GSR = "ENABLED" ;
defparam shift_ram_0_1_1.RESETMODE = "ASYNC" ;
defparam shift_ram_0_1_1.REGMODE_B = "NOREG" ;
defparam shift_ram_0_1_1.REGMODE_A = "NOREG" ;
defparam shift_ram_0_1_1.DATA_WIDTH_B = 9 ;
defparam shift_ram_0_1_1.DATA_WIDTH_A = 9 ;
DP8KC shift_ram_0_1_1 (.DIA8(Data[26]), .DIA7(Data[25]), .DIA6(Data[24]),
.DIA5(Data[23]), .DIA4(Data[22]), .DIA3(Data[21]), .DIA2(Data[20]),
.DIA1(Data[19]), .DIA0(Data[18]), .ADA12(scuba_vlo), .ADA11(scuba_vlo),
.ADA10(scuba_vlo), .ADA9(scuba_vlo), .ADA8(scuba_vlo), .ADA7(scuba_vlo),
.ADA6(scuba_vlo), .ADA5(scuba_vlo), .ADA4(Address[1]), .ADA3(Address[0]),
.ADA2(scuba_vlo), .ADA1(scuba_vlo), .ADA0(scuba_vhi), .CEA(ClockEn),
.OCEA(ClockEn), .CLKA(Clock), .WEA(WE), .CSA2(scuba_vlo), .CSA1(scuba_vlo),
.CSA0(scuba_vlo), .RSTA(Reset), .DIB8(Data[35]), .DIB7(Data[34]),
.DIB6(Data[33]), .DIB5(Data[32]), .DIB4(Data[31]), .DIB3(Data[30]),
.DIB2(Data[29]), .DIB1(Data[28]), .DIB0(Data[27]), .ADB12(scuba_vhi),
.ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo), .ADB8(scuba_vlo),
.ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo), .ADB4(Address[1]),
.ADB3(Address[0]), .ADB2(scuba_vlo), .ADB1(scuba_vlo), .ADB0(scuba_vhi),
.CEB(ClockEn), .OCEB(ClockEn), .CLKB(Clock), .WEB(WE), .CSB2(scuba_vlo),
.CSB1(scuba_vlo), .CSB0(scuba_vlo), .RSTB(Reset), .DOA8(Q[26]),
.DOA7(Q[25]), .DOA6(Q[24]), .DOA5(Q[23]), .DOA4(Q[22]), .DOA3(Q[21]),
.DOA2(Q[20]), .DOA1(Q[19]), .DOA0(Q[18]), .DOB8(Q[35]), .DOB7(Q[34]),
.DOB6(Q[33]), .DOB5(Q[32]), .DOB4(Q[31]), .DOB3(Q[30]), .DOB2(Q[29]),
.DOB1(Q[28]), .DOB0(Q[27]))
/* synthesis MEM_LPC_FILE="shift_ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam shift_ram_0_2_0.INIT_DATA = "STATIC" ;
defparam shift_ram_0_2_0.ASYNC_RESET_RELEASE = "SYNC" ;
defparam shift_ram_0_2_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam shift_ram_0_2_0.CSDECODE_B = "0b000" ;
defparam shift_ram_0_2_0.CSDECODE_A = "0b000" ;
defparam shift_ram_0_2_0.WRITEMODE_B = "NORMAL" ;
defparam shift_ram_0_2_0.WRITEMODE_A = "NORMAL" ;
defparam shift_ram_0_2_0.GSR = "ENABLED" ;
defparam shift_ram_0_2_0.RESETMODE = "ASYNC" ;
defparam shift_ram_0_2_0.REGMODE_B = "NOREG" ;
defparam shift_ram_0_2_0.REGMODE_A = "NOREG" ;
defparam shift_ram_0_2_0.DATA_WIDTH_B = 9 ;
defparam shift_ram_0_2_0.DATA_WIDTH_A = 9 ;
DP8KC shift_ram_0_2_0 (.DIA8(Data[44]), .DIA7(Data[43]), .DIA6(Data[42]),
.DIA5(Data[41]), .DIA4(Data[40]), .DIA3(Data[39]), .DIA2(Data[38]),
.DIA1(Data[37]), .DIA0(Data[36]), .ADA12(scuba_vlo), .ADA11(scuba_vlo),
.ADA10(scuba_vlo), .ADA9(scuba_vlo), .ADA8(scuba_vlo), .ADA7(scuba_vlo),
.ADA6(scuba_vlo), .ADA5(scuba_vlo), .ADA4(Address[1]), .ADA3(Address[0]),
.ADA2(scuba_vlo), .ADA1(scuba_vlo), .ADA0(scuba_vhi), .CEA(ClockEn),
.OCEA(ClockEn), .CLKA(Clock), .WEA(WE), .CSA2(scuba_vlo), .CSA1(scuba_vlo),
.CSA0(scuba_vlo), .RSTA(Reset), .DIB8(scuba_vlo), .DIB7(scuba_vlo),
.DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), .DIB3(scuba_vlo),
.DIB2(Data[47]), .DIB1(Data[46]), .DIB0(Data[45]), .ADB12(scuba_vhi),
.ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo), .ADB8(scuba_vlo),
.ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo), .ADB4(Address[1]),
.ADB3(Address[0]), .ADB2(scuba_vlo), .ADB1(scuba_vlo), .ADB0(scuba_vhi),
.CEB(ClockEn), .OCEB(ClockEn), .CLKB(Clock), .WEB(WE), .CSB2(scuba_vlo),
.CSB1(scuba_vlo), .CSB0(scuba_vlo), .RSTB(Reset), .DOA8(Q[44]),
.DOA7(Q[43]), .DOA6(Q[42]), .DOA5(Q[41]), .DOA4(Q[40]), .DOA3(Q[39]),
.DOA2(Q[38]), .DOA1(Q[37]), .DOA0(Q[36]), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(Q[47]), .DOB1(Q[46]), .DOB0(Q[45]))
/* synthesis MEM_LPC_FILE="shift_ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
// exemplar begin
// exemplar attribute shift_ram_0_0_2 MEM_LPC_FILE shift_ram.lpc
// exemplar attribute shift_ram_0_0_2 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute shift_ram_0_1_1 MEM_LPC_FILE shift_ram.lpc
// exemplar attribute shift_ram_0_1_1 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute shift_ram_0_2_0 MEM_LPC_FILE shift_ram.lpc
// exemplar attribute shift_ram_0_2_0 MEM_INIT_FILE INIT_ALL_0s
// exemplar end
endmodule