ADVERTENCIA: Xst: 1293 - FF / Latch clkDiv / counter_1 tiene un valor constante de 0 en el bloque DAC. Este FF / Latch se recortará durante el proceso de optimización

-3

Recibí una advertencia como esta:

WARNING:Xst:1293 - FF/Latch <clkDiv/counter_1> has a constant value of 0 in block <DAC>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <clkDiv/counter_1> has a constant value of 0 in block <DAC>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <clkDiv/counter_1> has a constant value of 0 in block <DAC>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <clkDiv/counter_1> has a constant value of 0 in block <DAC>. This FF/Latch will be trimmed during the optimization process.

¿Hay algo mal en mi código? ¡Gracias!

library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;

entity DAC is
    port(
        CLK: in std_logic;
        CLK2: inout std_logic;
        CS: out std_logic;
        MOSI: out std_logic
    );
end DAC;

architecture behavioral of DAC is
    signal reg : std_logic_vector (23 downto 0) :="100001100011100000000001";
    signal counter_G : integer range 0 to 24 := 0;
    signal CS_S : std_logic := '1';
    signal mosi_S : std_logic := '0';
    constant DELAY:integer := 2; 
begin
    clkDiv : entity work.ClockDivider(Behavioral) 
        generic map(DELAY => DELAY)
        port map (CLK, CLK2);        

    Senddata : process(CLK2, counter_G) 
    begin
        if falling_edge(CLK2) then
            counter_G <= counter_G + 1;
            if counter_G <24 then    
                CS_S <= '0';
                mosi_S <= reg(23);
                reg <= reg(22 downto 0) & reg(23);
            else
               CS_S <= '1';
               counter_G <=0;
            end if;        
        end if;
    end process Senddata;

    CS <= CS_S;
    MOSI <= mosi_S;
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ClockDivider is
    GENERIC (DELAY: integer := 16 );
    PORT 
    ( 
        CLK : in  STD_LOGIC;
        CLK_OUT : out  STD_LOGIC := '0'
    );
end ClockDivider;

architecture Behavioral of ClockDivider is
begin    
    process(CLK)
        variable counter : integer range 0 to DELAY := 0;
    begin
        if(CLK'event AND CLK='1') then
            counter := counter + 1;
            if counter = DELAY / 2 then
                CLK_OUT <= '0';
            elsif counter = DELAY then
                counter := 0;
                CLK_OUT <= '1';
            end if;
        end if;
    end process;
end Behavioral;
    
pregunta Yuan Cao

1 respuesta

0

No utilice un tipo inout para CLK2 . Utilice VHDL-2008 o use una variable temporal.

Entonces, counter es probable que se restablezca a 0 cada vez que se dispare el proceso del divisor de reloj. No uses variables como esta: usa señales en su lugar. Por ejemplo,

architecture Behavioral of ClockDivider is
    signal counter : natural range 0 to DELAY := 0;
begin    
    clk_div_proc: process(CLK)
    begin
        if rising_edge(CLK) then
            if counter < DELAY then
                counter <= counter + 1;
            else
                counter <= 0;
            end if;
            if counter < DELAY/2 then
                CLK_OUT <= '1';
            else
                CLK_OUT <= '0';
            end if;
        end if;
    end process;
end Behavioral;
    
respondido por el JHBonarius

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