Estoy obteniendo salidas de mi hardware como toda alta impedancia (ZZZZZ). Intenté sintetizar el código y obtuve estas advertencias. Creo que podría haber un problema en el banco de pruebas que estoy intentando ejecutar.
source div_restoring.tcl -notrace
Command: synth_design -top div_restoring -part xc7z010clg400-3
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 8248
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Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 357.441 ; gain = 99.344
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INFO: [Synth 8-6157] synthesizing module 'div_restoring' [C:/Users/ERis/LAB_THREE/LAB_THREE.srcs/sources_1/new/div_restoring.v:24]
WARNING: [Synth 8-5788] Register reg_q_reg in module div_restoring is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/ERis/LAB_THREE/LAB_THREE.srcs/sources_1/new/div_restoring.v:38]
WARNING: [Synth 8-5788] Register reg_b_reg in module div_restoring is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/ERis/LAB_THREE/LAB_THREE.srcs/sources_1/new/div_restoring.v:38]
WARNING: [Synth 8-5788] Register reg_r_reg in module div_restoring is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/ERis/LAB_THREE/LAB_THREE.srcs/sources_1/new/div_restoring.v:38]
WARNING: [Synth 8-5788] Register count_reg in module div_restoring is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/ERis/LAB_THREE/LAB_THREE.srcs/sources_1/new/div_restoring.v:60]
INFO: [Synth 8-6155] done synthesizing module 'div_restoring' (1#1) [C:/Users/ERis/LAB_THREE/LAB_THREE.srcs/sources_1/new/div_restoring.v:24]
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Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 411.883 ; gain = 153.785
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Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 411.883 ; gain = 153.785
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Start Loading Part and Timing Information
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Loading part: xc7z010clg400-3
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 411.883 ; gain = 153.785
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INFO: [Device 21-403] Loading part xc7z010clg400-3
INFO: [Synth 8-5546] ROM "busy" won't be mapped to RAM because it is too sparse
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 411.883 ; gain = 153.785
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Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
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Start RTL Component Statistics
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Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 1
2 Input 5 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
16 Bit Registers := 2
5 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 16 Bit Muxes := 2
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
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Finished RTL Component Statistics
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Start RTL Hierarchical Component Statistics
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Hierarchical RTL Component report
Module div_restoring
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 1
2 Input 5 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
16 Bit Registers := 2
5 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 16 Bit Muxes := 2
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
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Finished RTL Hierarchical Component Statistics
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Start Part Resource Summary
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Part Resources:
DSPs: 80 (col length:40)
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
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Finished Part Resource Summary
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No constraint files found.
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Start Cross Boundary and Area Optimization
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Warning: Parallel synthesis criteria is not met
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 551.531 ; gain = 293.434
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Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 551.531 ; gain = 293.434
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Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
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Start Technology Mapping
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Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 551.531 ; gain = 293.434
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Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
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Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 551.531 ; gain = 293.434
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Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 551.531 ; gain = 293.434
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Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
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Start Rebuilding User Hierarchy
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 551.531 ; gain = 293.434
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 551.531 ; gain = 293.434
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 551.531 ; gain = 293.434
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 551.531 ; gain = 293.434
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Start Writing Synthesis Report
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Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |BUFG | 1|
|2 |CARRY4 | 5|
|3 |LUT1 | 3|
|4 |LUT2 | 20|
|5 |LUT3 | 51|
|6 |LUT4 | 1|
|7 |LUT5 | 2|
|8 |FDCE | 2|
|9 |FDRE | 69|
|10 |IBUF | 51|
|11 |OBUF | 55|
+------+-------+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 260|
+------+---------+-------+------+
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 551.531 ; gain = 293.434
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Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 551.531 ; gain = 293.434
Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 551.531 ; gain = 293.434
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 56 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 655.586 ; gain = 410.492
WARNING: [Constraints 18-5210] No constraint will be written out.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ERis/LAB_THREE/LAB_THREE.runs/synth_3/div_restoring.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file div_restoring_utilization_synth.rpt -pb div_restoring_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.100 . Memory (MB): peak = 655.586 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Mon Jul 2 21:47:59 2018...
el código fuente es
'timescale 1ns / 1ps
module div_restoring (a,b,start,clk,clrn,q,r,busy,ready,count);
input [31:0] a; // dividend
input [15:0] b; // divisor
input start; // start
input clk, clrn; // clk,reset
output [31:0] q; // quotient
output [15:0] r; // remainder
output reg busy; // busy
output reg ready; // ready
output [4:0] count; // counter
reg [31:0] reg_q; // reg_q 32 bit
reg [15:0] reg_r; // reg_r 16 bit
reg [15:0] reg_b; // reg_b 16 bit
reg [4:0] count;
wire [16:0] sub_out = {reg_r,reg_q[31]} - {1'b0,reg_b}; // concatination and substraction
wire [15:0] mux_out = sub_out[16]? // restoring
{reg_r[14:0],reg_q[31]} : sub_out[15:0]; // or not
assign q = reg_q;
assign r = reg_r;
always @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
busy <= 0;
ready <= 0;
end
else
begin
if (start)
begin
reg_q <= a; // load a
reg_b <= b; // load b
reg_r <= 0;
busy <= 1;
ready <= 0;
count <= 0;
end
else if (busy)
begin
reg_q <= {reg_q[30:0],sub_out[16]}; // << 1
reg_r <= mux_out;
count <= count + 5'b1; // counter++
if (count == 5'h1f)
begin // finished
busy <= 0;
ready <= 1; // q,r ready
end
end
end
end
endmodule
el banco de pruebas que estoy usando es
module test_tb;
reg [31:0] a;
reg [15:0] b;
reg start,clk_200,clrn;
wire [31:0] q;
wire [15:0] r;
wire busy,ready;
wire [4:0] count;
// instantiate device under test
div_restoring dut(
.a(a),
.b(b),
.start(start),
.clk(clk_200),
.clrn(clrn)
);
// generate 200 mhz clock
initial
begin
clk_200 = 1;
start = 0;
clrn = 0;
assign a = 32'H0;
assign b = 16'H0;
#5 start = 1;
clrn = 1;
assign a = 32'H4c7f228a;
assign b = 16'H6a0e;
#10 start = 0;
end
always
#5 clk_200 = ~clk_200;
endmodule