Xilinx ISim Post-Route Simulation produce un resultado inesperado

Estoy tratando de observar la diferencia de retardo de propagación entre un sumador de rizado de acarreo de 4 bits frente a un sumador de avance de acarreo de 4 bits.

La arquitectura VHDL del sumador carry ripple es:

entity adder4 is
    Port ( Cin : in  STD_LOGIC;
           x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           Cout : out  STD_LOGIC);
end adder4;

architecture Behavioral of adder4 is
    component fullAdder    
        Port ( Cin : in  STD_LOGIC;
           x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           s : out  STD_LOGIC;
           Cout : out  STD_LOGIC);
  end component;   
  SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;      
begin
    stage0: fullAdder PORT MAP (Cin, X(0), Y(0), S(0), C(1));
    stage1: fullAdder PORT MAP (C(1), X(1), Y(1), S(1), C(2));
    stage2: fullAdder PORT MAP (C(2), X(2), Y(2), S(2), C(3));
    stage3: fullAdder PORT MAP (C(3), X(3), Y(3), S(3), Cout);
end Behavioral;

Y la arquitectura del sumador de seguimiento anticipado es:

entity adder4LookAHead is
    Port ( Cin : in  STD_LOGIC;
           X : in  STD_LOGIC_VECTOR (3 downto 0);
           Y : in  STD_LOGIC_VECTOR (3 downto 0);
           S : out  STD_LOGIC_VECTOR (3 downto 0);
           Cout : out  STD_LOGIC);
end adder4LookAHead;

architecture Behavioral of adder4LookAHead is
    signal c : STD_LOGIC_VECTOR (3 downto 1);
    signal g : STD_LOGIC_VECTOR (3 downto 0);
    signal p : STD_LOGIC_VECTOR (3 downto 0);

begin
    g(0) <= x(0) and y(0);
    p(0) <= x(0) or y(0);
    c(1) <= g(0) or (p(0) and Cin);

    g(1) <= x(1) and y(1);
    p(1) <= x(1) or y(1);
    c(2) <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and Cin);

    g(2) <= x(2) and y(2);
    p(2) <= x(2) or y(2);
    c(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0)) or 
        (p(2) and p(1) and p(0) and Cin);

    g(3) <= x(3) and y(3);
    p(3) <= x(3) or y(3);
    Cout <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1)) or 
        (p(3) and p(2) and p(1) and g(0)) or 
        (p(3) and p(2) and p(1) and p(0) and Cin);

    S(0) <= (x(0) xor y(0)) xor Cin;
    S(1) <= (x(1) xor y(1)) xor c(1);
    S(2) <= (x(2) xor y(2)) xor c(2);
    S(3) <= (x(3) xor y(3)) xor c(3);

end Behavioral;

Ambos sumadores producen una salida correcta en la simulación de comportamiento. Lo único extraño es que para la simulación posterior a la ruta, las salidas tienen exactamente el mismo retardo de propagación. mientras espero ver un retardo de propagación diferente.

¿Qué me estoy perdiendo aquí?