VHDL - Problemas con el flip flop estructural J-K

Quiero implementar un flip-flop J-K sensible al nivel en modo estructural usando un pestillo R-S. Este es mi código:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ff_jk_m is
Port ( J : in  STD_LOGIC;
       K : in  STD_LOGIC;
       clk : in  STD_LOGIC;
       Q : out  STD_LOGIC;
       Qn : out  STD_LOGIC);
end ff_jk_m;

architecture Structural of ff_jk_m is
    component latch_rs_enabled_m is
    generic(active_high : std_logic := '1');
    Port ( R : in  STD_LOGIC;
       S : in  STD_LOGIC;
       E : in  STD_LOGIC;
       Q : out  STD_LOGIC;
       Qn : out  STD_LOGIC);
    end component;
signal sS, sR, sQ, sQn: std_logic;

begin

sR <= K and sQ;
sS <= J and sQn;
Q <= sQ;
Qn <= sQn;
ff_rs : latch_rs_enabled_m port map(
    R => sR,
    S => sS,
    E => clk,
    Q => sQ,
    Qn => sQn);

end Structural;

Pestillo R-S con habilitación

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity latch_rs_enabled_m is
 generic(active_high : std_logic := '1');
 Port ( R : in  STD_LOGIC;
       S : in  STD_LOGIC;
       E : in  STD_LOGIC;
       Q : out  STD_LOGIC;
       Qn : out  STD_LOGIC);
end latch_rs_enabled_m;

architecture Structural of latch_rs_enabled_m is
 component rs_latch_m is
 generic(nor_nand : std_logic:='1');
 Port ( R : in  STD_LOGIC;
       S : in  STD_LOGIC;
       Q : out  STD_LOGIC;
       Qn : out  STD_LOGIC);
 end component; 

signal s1 : std_logic := '0';
signal r1 : std_logic := '0';

begin

latch_nor : if(active_high = '1') generate

     s1 <= S and E;
     r1 <= R and E;
     rs_nor : rs_latch_m generic map('1') port map(
        S => s1,
        R => r1,
        Q => Q,
        Qn => Qn);
end generate;

latch_nand : if(active_high = '0') generate
     s1 <= S nand E;
     r1 <= R nand E;
     rs_nand : rs_latch_m generic map('0') port map(
        S => s1,
        R => r1,
        Q => Q,
        Qn => Qn);
end generate;

end Structural;

Pestillo R-S

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rs_latch_m is
 generic(nor_nand : std_logic:='0');
 Port ( R : in  STD_LOGIC;
       S : in  STD_LOGIC;
       Q : out  STD_LOGIC;
       Qn : out  STD_LOGIC);
end rs_latch_m;

architecture Structural of rs_latch_m is
 signal sq, sqn : std_logic;

begin
 Q <= sq;
 Qn <= sqn;

latch_nor : if(nor_nand ='1') generate
                sq <= R nor sqn;
                sqn <= S nor sq;
                end generate;

latch_nand : if(nor_nand ='0') generate
                sqn <= R nand sq;
                sq <= S nand sqn;
                end generate;

end Structural; 

J-K flip flop testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY ff_jk_tb IS
END ff_jk_tb;

ARCHITECTURE behavior OF ff_jk_tb IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT ff_jk_m
PORT(
     J : IN  std_logic;
     K : IN  std_logic;
     clk : IN  std_logic;
     Q : out  std_logic;
     Qn : out  std_logic
    );
END COMPONENT;


 --Inputs
   signal J : std_logic := '0';
   signal K : std_logic := '0';
   signal clk : std_logic := '0';

 --Outputs
   signal Q : std_logic;
   signal Qn : std_logic;

 -- Clock period definitions
   constant clk_period : time := 200 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
 uut: ff_jk_m PORT MAP (
      J => J,
      K => K,
      clk => clk,
      Q => Q,
      Qn => Qn
    );

 -- Clock process definitions
    clk_process :process
     begin
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
     end process;


  -- Stimulus process
    stim_proc: process
     begin      
  -- hold reset state for 100 ns.
  wait for 100 ns;  
    J <= '1';
    wait for 50 ns;
    K <= '1';
    wait for 40 ns;
    J <= '0';
    wait for 60 ns;
    K <= '0';
    wait for 100 ns;
    K <= '1';
    wait for 60 ns;
    J <= '1';
    K <= '0';
  wait for clk_period*10;

  -- insert stimulus here 

  wait;
 end process;

 END;

Durante una simulación con ISim, en modo Lite, las salidas Q y Qn siempre están indefinidas. ¿Qué pasa con mi código?

P.S: R-S latch habilitado funciona correctamente