ConstruíunaALUusandoModelSim"Verilog", compilé el código correctamente, pero no puedo obtener ninguna señal en ninguno (ans, y, cero), ¿puedes decirme qué está mal con mi código? Gracias!
///////////////////////// 2-1 MUX /////////////////////////
module MUX2_1(input [31:0] d0, d1,
input f2,
output reg [31:0] y);
always @* begin
case(f2)
2'b0: y = d0;
2'b1: y = d1;
endcase
end
endmodule
///////////////////////// 4-1 MUX /////////////////////////
module MUX4_1(input [31:0] d0, d1, d2, d3,
input [1:0] f,
output reg [31:0] y);
always @* begin
case(f)
2'b00: y = d0;
2'b01: y = d1;
2'b10: y = d2;
2'b11: y = d3;
endcase
end
endmodule
///////////////////////// 32-bit Adder /////////////////////////
module Adder_32(input [31:0]a, b,
output reg [31:0]sum);
always @ * begin
sum = a+b;
end
endmodule
///////////////////////// 32-bit Subtractor /////////////////////////
module Subtr_32(input [31:0] a, b,
output reg[31:0] diff);
always @ * begin
diff = a-b;
end
endmodule
///////////////////////// SLT /////////////////////////
module SLT(input [31:0] a, b,
output reg[31:0] ans);
always @* begin
if(a+b == 'h1xxxxxxx) /* if a < b */
ans = 'h00000001;
else /* if a > b */
ans = 'h00000000; end
endmodule
///////////////////////// 32-bit AND /////////////////////////
module AND(input [31:0] a, b,
output reg [31:0] y);
always @ * begin
y = a & b;
end
endmodule
///////////////////////// 32-bit OR /////////////////////////
module OR(input [31:0] a, b,
output reg [31:0] y);
always @ * begin
y = a | b;
end
endmodule
///////////////////////// ALU /////////////////////////
module alu(input [31:0] a, b,
input [2:0] f,
output reg [31:0] y,
output reg zero);
wire f2 = f[2];
wire f10 = f[1:0];
wire [31:0] mux2_1, data_0, data_1, data_2, data_3, ans;
MUX2_1 m1(b, ~b, f2, mux2_1);
AND and1(mux2_1, a, data_0);
OR or1(mux2_1, a, data_1);
Adder_32 add1(mux2_1, a, data_2);
SLT slt1(mux2_1, a, data_3);
MUX4_1 m2(data_0, data_1, data_2, data_3, f10, ans);
always @ * begin
y = ans;
if(y==0)
zero = 1;
else
zero = 0;
end
endmodule