Estoy haciendo JKnRnS maestro esclavo flip-flop, aquí está mi código:
library IEEE;
use IEEE.std_logic_1164.all;
entity JKnRnS is
port(
C : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
nR : in STD_LOGIC;
nS : in STD_LOGIC;
Q : inout STD_LOGIC;
nQ : inout STD_LOGIC
);
end entity;
architecture JKnRnS of JKnRnS is
signal Q_int: std_logic := '1';
signal NQ_int: std_logic := '0';
signal a,b,c1,d,f,e,notC: STD_LOGIC;
begin
a<=not(C and J and nS and NQ_int);
c1<=not(d and a and nS);
d <= not(nR and b and c1);
b <= not(Q_int and nR and K and C);
e <= not(notC and c1);
f <= not(d and notC);
Q_int <= not(NQ_int and e and nS);
NQ_int <= not(nR and f and Q_int);
notC <= not(C);
Q<=Q_int;
nQ<=NQ_int;
end architecture;
que funciona bien, pero cuando lo cambio a:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.all;
entity nand_3 is
generic (t_rise: TIME:= 0 ns; t_fall : TIME:= 0 ns);
port(
in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
in3 : in STD_LOGIC;
out1: out STD_LOGIC
);
end entity;
architecture nand_3 of nand_3 is
begin
process (in1, in2, in3) is
begin
out1 <= not(in1 and in2 and in3);
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity nand_4 is
port(
in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
in3 : in STD_LOGIC;
in4 : in STD_LOGIC;
out1 : out STD_LOGIC
);
end entity;
architecture nand_4 of nand_4 is
begin
process (in1, in2, in3, in4) is
begin
out1<=not(in1 and in2 and in3 and in4);
end process;
end architecture;
library IEEE;
use IEEE.std_logic_1164.all;
entity JKnRnS is
port(
C : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
nR : in STD_LOGIC;
nS : in STD_LOGIC;
Q : inout STD_LOGIC;
nQ : inout STD_LOGIC
);
end entity;
architecture JKnRnS of JKnRnS is
signal Q_int: std_logic := '1';
signal NQ_int: std_logic := '0';
signal a,b,c1,d,f,e,notC: STD_LOGIC;
begin
E1: entity work.nand_4(nand_4)
port map(in1=>C, in2=>J, in3=>nS, in4=>NQ_int, out1=>a);
E2: entity work.nand_3(nand_3)
port map(in1=>d, in2=>a, in3=>nS, out1=>c1);
d <= not(nR and b and c1);
b <= not(Q_int and nR and K and C);
e <= not(notC and c1);
f <= not(d and notC);
Q_int <= not(NQ_int and e and nS);
NQ_int <= not(nR and f and Q_int);
notC <= not(C);
Q<=Q_int;
nQ<=NQ_int;
end architecture;
Me sale un error: KERNEL: Error: KERNEL_0160 Desbordamiento de recuento de Delta. Aumente el límite de iteración utilizando el argumento -i para asim o la entrada coincidente en las preferencias de simulación. ¿Qué está mal aquí?