Estoy escribiendo un código VHDL para algunos propósitos básicos de procesamiento de imágenes y obtengo una advertencia "null assigment (en declerations de señales) / puerto (en declaraciones de componentes) ignorada" en mi código. Aquí está el módulo superior del código. Las partes problemáticas están marcadas con "XXX". Para explicar el código, tengo otro módulo llamado imagen en el que declaré un paquete de matriz 2D llamado pic_array y su tipo es picture_array. En el sub-módulo de imagen tengo 2 matrices 2D de tipo de matriz de imagen que se rellenan con 12 bits. Creé un componente del sub-módulo de imagen e intenté inicializar algunas señales a continuación. Sin embargo, no parecen estar inicializados. Mi pregunta es: ¿por qué recibo esta advertencia y cómo puedo resolverla?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.pic_array.all;
entity vga_core is
generic (
COLOR_BIT : integer := 4);
port (
raw_clk : in std_logic;
rst : in std_logic;
data_r : out std_logic_vector(COLOR_BIT-1 downto 0);
data_g : out std_logic_vector(COLOR_BIT-1 downto 0);
data_b : out std_logic_vector(COLOR_BIT-1 downto 0);
hs_out : out std_logic;
vs_out : out std_logic
);
end vga_core;
constant RES_H : integer := 640;
constant RES_V : integer := 480;
constant H_FRONT_PORCH : integer := 16;
constant H_SYNC_TIME : integer := 96;
constant H_BACK_PORCH : integer := 48;
constant V_FRONT_PORCH : integer := 11;
constant V_SYNC_TIME : integer := 2;
constant V_BACK_PORCH : integer := 31;
constant TOTAL_H : integer := RES_H + H_FRONT_PORCH + H_SYNC_TIME + H_BACK_PORCH; -- 800
constant TOTAL_V : integer := RES_V + V_FRONT_PORCH + V_SYNC_TIME + V_BACK_PORCH; -- 524
signal COUNTER_H : integer range 0 to TOTAL_H := 0; -- 0 to 800
signal COUNTER_V : integer range 0 to TOTAL_V := 0; -- 0 to 524
signal NEW_LINE : std_logic := '0';
signal h_visible : std_logic := '0';
signal v_visible : std_logic := '0';
signal visible : std_logic := '0';
signal clk : std_logic := '0';
signal temporal: std_logic := '0';
signal counter : integer range 0 to 1 := 0;
signal def_pic : picture_array(40 downto 289,80 downto 329) := (others => (others => "0")); "XXX"
signal processed_pic : picture_array(350 downto 599,80 downto 329) := (others => (others => "0")); "XXX"
signal processed_pic2: picture_array(350 downto 599,80 downto 329) := processed_pic; "XXX"
signal pos_x : integer range 0 to 2047 := 0;
signal pos_y : integer range 0 to 2047 := 0;
signal vgaData : std_logic_vector(3*COLOR_BIT-1 downto 0) := "000000000000";
component picture
port (def_pic : inout picture_array (40 downto 289,80 downto 329);"XXX"
processed_pic : inout picture_array (350 downto 599,80 downto 329));"XXX"
end component;
begin
u1: picture port map (def_pic => def_pic,
processed_pic => processed_pic);
frequency_divider: process (raw_clk, rst) begin
if (rst = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(raw_clk) then
if (counter = 1) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk <= temporal;
CNT_H : process (clk, rst) is
begin -- process CNT_H
if rst = '1' then
COUNTER_H <= 0;
NEW_LINE <= '0';
elsif clk'event and clk = '1' then
if (COUNTER_H = TOTAL_H-1) then
COUNTER_H <= 0;
NEW_LINE <= '1';
else
COUNTER_H <= COUNTER_H + 1;
NEW_LINE <= '0';
end if;
end if;
end process CNT_H;
CNT_V : process (clk, rst) is
begin -- process CNT_V
if rst = '1' then
COUNTER_V <= 0;
elsif clk'event and clk = '1' then
if (NEW_LINE = '1') then
if (COUNTER_V = TOTAL_V-1) then
COUNTER_V <= 0;
else
COUNTER_V <= COUNTER_V + 1;
end if;
end if;
end if;
end process CNT_V;
SYNC_H : process (clk, rst) is
begin -- process SYNC_H
if rst = '1' then
hs_out <= '0';
elsif clk'event and clk = '1' then
if (COUNTER_H < H_SYNC_TIME) then
hs_out <= '0';
else
hs_out <= '1';
end if;
end if;
end process SYNC_H;
SYNC_V : process (clk, rst) is
begin -- process SYNC_V
if rst = '1' then
vs_out <= '0';
elsif clk'event and clk = '1' then
if (COUNTER_V < V_SYNC_TIME) then
vs_out <= '0';
else
vs_out <= '1';
end if;
end if;
end process SYNC_V;
AREA_H : process (clk, rst) is
begin -- process AREA_H
if rst = '1' then
h_visible <= '0';
elsif clk'event and clk = '1' then
if (COUNTER_H > H_SYNC_TIME + H_BACK_PORCH - 1) and (COUNTER_H < TOTAL_H - H_FRONT_PORCH) then
h_visible <= '1';
if ((COUNTER_H - (H_SYNC_TIME + H_BACK_PORCH)) <641) then
pos_x <= COUNTER_H - (H_SYNC_TIME + H_BACK_PORCH);
end if;
else
h_visible <= '0';
end if;
end if;
end process AREA_H;
AREA_V : process (clk, rst) is
begin -- process AREA_V
if rst = '1' then
v_visible <= '0';
elsif clk'event and clk = '1' then
if (COUNTER_V > V_SYNC_TIME + V_BACK_PORCH - 1) and (COUNTER_V < TOTAL_V - V_FRONT_PORCH) then
v_visible <= '1';
if ((COUNTER_V - (V_SYNC_TIME + V_BACK_PORCH)) < 481) then
pos_y <= COUNTER_V - (V_SYNC_TIME + V_BACK_PORCH);
end if;
else
v_visible <= '0';
end if;
end if;
end process AREA_V;
visible <= h_visible and v_visible;
SHOW : process (clk, rst) is
begin -- process SHOW
if rst = '1' then
processed_pic2 <= processed_pic;
elsif clk'event and clk = '1' then
if (visible = '1') and ( pos_x < 290) and (pos_y <330) and (pos_x > 39) and (pos_y > 79) then
vgaData <= def_pic(pos_x,pos_y);
data_r <= vgaData(3*COLOR_BIT-1 downto 2*COLOR_BIT);
data_g <= vgaData(2*COLOR_BIT-1 downto COLOR_BIT);
data_b <= vgaData(COLOR_BIT-1 downto 0);
elsif (visible = '1') and ( pos_x < 651) and (pos_y < 331) and (pos_x > 349) and (pos_y > 79) then
vgaData <= processed_pic2(pos_x,pos_y);
data_r <= vgaData(3*COLOR_BIT-1 downto 2*COLOR_BIT);
data_g <= vgaData(2*COLOR_BIT-1 downto COLOR_BIT);
data_b <= vgaData(COLOR_BIT-1 downto 0);
else
vgaData <= "000000001111"; -- mavi
data_r <= vgaData(3*COLOR_BIT-1 downto 2*COLOR_BIT);
data_g <= vgaData(2*COLOR_BIT-1 downto COLOR_BIT);
data_b <= vgaData(COLOR_BIT-1 downto 0);
end if;
end if;
end process SHOW;
end VGA;