Estoy implementando GTWizard (configuración GTH, JESD204 para PHY, versión: 3.6) & JESD204 RX IP Core. VAIVADO: 2017.4, IC: Virtex-7
Pero, RX_sync & m_axis_rx_valid de JESD204 IP Core LOW .....
¿Por qué va a LOW a veces?
por favor ayúdame.
El código de mi transceptor es el siguiente.
gtwizard_0 GTH_0 ( .soft_reset_rx_in (core_reset), .dont_reset_on_data_error_in (1'b1), .q5_clk1_gtrefclk_pad_n_in (refclk_n), .q5_clk1_gtrefclk_pad_p_in (refclk_p), .gt0_tx_fsm_reset_done_out (), .gt0_rx_fsm_reset_done_out (gt0_rx_fsm_reset_done_out_0), .gt0_data_valid_in (1'b1), .gt1_tx_fsm_reset_done_out (), .gt1_rx_fsm_reset_done_out (gt0_rx_fsm_reset_done_out_1), .gt1_data_valid_in (1'b1),
.gt0_rxusrclk_out(),
.gt0_rxusrclk2_out(core_clk_i_i),
.gt1_rxusrclk_out(),
.gt1_rxusrclk2_out(verfying_rxusrclk2),
//_________________________________________________________________________
//GT0 (X1Y20)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
.gt0_cpllfbclklost_out (), // output wire gt0_cpllfbclklost_out
.gt0_cplllock_out (), // output wire gt0_cplllock_out
.gt0_cpllreset_in (), // input wire gt0_cpllreset_in
//------------------------ Channel - Clocking Ports ------------------------
.gt0_gtnorthrefclk0_in (), // input wire gt0_gtnorthrefclk0_in
.gt0_gtnorthrefclk1_in (), // input wire gt0_gtnorthrefclk1_in
.gt0_gtsouthrefclk0_in (), // input wire gt0_gtsouthrefclk0_in
.gt0_gtsouthrefclk1_in (), // input wire gt0_gtsouthrefclk1_in
//-------------------------- Channel - DRP Ports --------------------------
.gt0_drpaddr_in (9'd0), // input wire [8:0] gt0_drpaddr_in
.gt0_drpdi_in (16'd0), // input wire [15:0] gt0_drpdi_in
.gt0_drpdo_out (), // output wire [15:0] gt0_drpdo_out
.gt0_drpen_in (1'b0), // input wire gt0_drpen_in
.gt0_drprdy_out (), // output wire gt0_drprdy_out
.gt0_drpwe_in (1'b0), // input wire gt0_drpwe_in
//----------------------------- Loopback Ports -----------------------------
.gt0_loopback_in (3'b000), // input wire [2:0] gt0_loopback_in
//---------------------------- Power-Down Ports ----------------------------
.gt0_rxpd_in (1'b0), // input wire [1:0] gt0_rxpd_in
.gt0_txpd_in (1'b1), // input wire [1:0] gt0_txpd_in
//------------------- RX Initialization and Reset Ports --------------------
.gt0_eyescanreset_in (core_reset), // input wire gt0_eyescanreset_in
.gt0_rxuserrdy_in (1'b1), // input wire gt0_rxuserrdy_in
//------------------------ RX Margin Analysis Ports ------------------------
.gt0_eyescandataerror_out (), // output wire gt0_eyescandataerror_out
.gt0_eyescantrigger_in (), // input wire gt0_eyescantrigger_in
//----------------------- Receive Ports - CDR Ports ------------------------
.gt0_rxcdrhold_in (), // input wire gt0_rxcdrhold_in
//----------------- Receive Ports - Digital Monitor Ports ------------------
.gt0_dmonitorout_out (), // output wire [14:0] gt0_dmonitorout_out
//---------------- Receive Ports - FPGA RX interface Ports -----------------
.gt0_rxdata_out (gt0_rx_rxdata), // output wire [31:0] gt0_rxdata_out
//----------------- Receive Ports - Pattern Checker Ports ------------------
.gt0_rxprbserr_out (), // output wire gt0_rxprbserr_out
.gt0_rxprbssel_in (), // input wire [2:0] gt0_rxprbssel_in
//----------------- Receive Ports - Pattern Checker ports ------------------
.gt0_rxprbscntreset_in (), // input wire gt0_rxprbscntreset_in
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
.gt0_rxdisperr_out (gt0_rx_rxdisperr), // output wire [3:0] gt0_rxdisperr_out
.gt0_rxnotintable_out (gt0_rx_rxnotintable), // output wire [3:0] gt0_rxnotintable_out
//---------------------- Receive Ports - RX AFE Ports ----------------------
.gt0_gthrxn_in (rxn[0]), // input wire gt0_gthrxn_in
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
.gt0_rxbufreset_in (core_reset), // input wire gt0_rxbufreset_in
.gt0_rxbufstatus_out (), // output wire [2:0] gt0_rxbufstatus_out
.gt0_rxstatus_out (), // output wire [2:0] gt0_rxstatus_out
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
.gt0_rxbyteisaligned_out (), // output wire gt0_rxbyteisaligned_out
.gt0_rxbyterealign_out (), // output wire gt0_rxbyterealign_out
.gt0_rxcommadet_out (), // output wire gt0_rxcommadet_out
.gt0_rxpcommaalignen_in (rxencommaalign_out), // input wire gt0_rxpcommaalignen_in
//------------------- Receive Ports - RX Equalizer Ports -------------------
.gt0_rxdfelpmreset_in (core_reset), // input wire gt0_rxdfelpmreset_in
.gt0_rxmonitorout_out (), // output wire [6:0] gt0_rxmonitorout_out
.gt0_rxmonitorsel_in (), // input wire [1:0] gt0_rxmonitorsel_in
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.gt0_rxoutclkfabric_out (), // output wire gt0_rxoutclkfabric_out
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gt0_gtrxreset_in (core_reset), // input wire gt0_gtrxreset_in
.gt0_rxpcsreset_in (core_reset), // input wire gt0_rxpcsreset_in
.gt0_rxpmareset_in (core_reset), // input wire gt0_rxpmareset_in
//---------------- Receive Ports - RX Margin Analysis ports ----------------
.gt0_rxlpmen_in (1'b1), // input wire gt0_rxlpmen_in
//--------------- Receive Ports - RX Polarity Control Ports ----------------
.gt0_rxpolarity_in (), // input wire gt0_rxpolarity_in
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
.gt0_rxchariscomma_out (), // output wire [3:0] gt0_rxchariscomma_out
.gt0_rxcharisk_out (gt0_rx_rxcharisk), // output wire [3:0] gt0_rxcharisk_out
//---------------------- Receive Ports -RX AFE Ports -----------------------
.gt0_gthrxp_in (rxp[0]), // input wire gt0_gthrxp_in
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.gt0_rxresetdone_out (rx_reset_done0), // output wire gt0_rxresetdone_out
//------------------- TX Initialization and Reset Ports --------------------
.gt0_gttxreset_in (1'b1), // input wire gt0_gttxreset_in
//-------------------- Transmit Ports - TX Buffer Ports --------------------
.gt0_txbufstatus_out (), // output wire [1:0] gt0_txbufstatus_out
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.gt0_txpcsreset_in (), // input wire gt0_txpcsreset_in
//GT1 (X1Y21)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
.gt1_cpllfbclklost_out (), // output wire gt1_cpllfbclklost_out
.gt1_cplllock_out (), // output wire gt1_cplllock_out
.gt1_cpllreset_in (), // input wire gt1_cpllreset_in
//------------------------ Channel - Clocking Ports ------------------------
.gt1_gtnorthrefclk0_in (), // input wire gt1_gtnorthrefclk0_in
.gt1_gtnorthrefclk1_in (), // input wire gt1_gtnorthrefclk1_in
.gt1_gtsouthrefclk0_in (), // input wire gt1_gtsouthrefclk0_in
.gt1_gtsouthrefclk1_in (), // input wire gt1_gtsouthrefclk1_in
//-------------------------- Channel - DRP Ports --------------------------
.gt1_drpaddr_in (9'd0), // input wire [8:0] gt1_drpaddr_in
.gt1_drpdi_in (16'd0), // input wire [15:0] gt1_drpdi_in
.gt1_drpdo_out (), // output wire [15:0] gt1_drpdo_out
.gt1_drpen_in (1'b0), // input wire gt1_drpen_in
.gt1_drprdy_out (), // output wire gt1_drprdy_out
.gt1_drpwe_in (1'b0), // input wire gt1_drpwe_in
//----------------------------- Loopback Ports -----------------------------
.gt1_loopback_in (3'b000), // input wire [2:0] gt1_loopback_in
//---------------------------- Power-Down Ports ----------------------------
.gt1_rxpd_in (1'b0), // input wire [1:0] gt1_rxpd_in
.gt1_txpd_in (1'b1), // input wire [1:0] gt1_txpd_in
//------------------- RX Initialization and Reset Ports --------------------
.gt1_eyescanreset_in (core_reset), // input wire gt1_eyescanreset_in
.gt1_rxuserrdy_in (1'b1), // input wire gt1_rxuserrdy_in
//------------------------ RX Margin Analysis Ports ------------------------
.gt1_eyescandataerror_out (), // output wire gt1_eyescandataerror_out
.gt1_eyescantrigger_in (), // input wire gt1_eyescantrigger_in
//----------------------- Receive Ports - CDR Ports ------------------------
.gt1_rxcdrhold_in (), // input wire gt1_rxcdrhold_in
//----------------- Receive Ports - Digital Monitor Ports ------------------
.gt1_dmonitorout_out (), // output wire [14:0] gt1_dmonitorout_out
//---------------- Receive Ports - FPGA RX interface Ports -----------------
.gt1_rxdata_out (gt1_rx_rxdata), // output wire [31:0] gt1_rxdata_out
//----------------- Receive Ports - Pattern Checker Ports ------------------
.gt1_rxprbserr_out (), // output wire gt1_rxprbserr_out
.gt1_rxprbssel_in (), // input wire [2:0] gt1_rxprbssel_in
//----------------- Receive Ports - Pattern Checker ports ------------------
.gt1_rxprbscntreset_in (), // input wire gt1_rxprbscntreset_in
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
.gt1_rxdisperr_out (gt1_rx_rxdisperr), // output wire [3:0] gt1_rxdisperr_out
.gt1_rxnotintable_out (gt1_rx_rxnotintable), // output wire [3:0] gt1_rxnotintable_out
//---------------------- Receive Ports - RX AFE Ports ----------------------
.gt1_gthrxn_in (rxn[1]), // input wire gt1_gthrxn_in
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
.gt1_rxbufreset_in (core_reset), // input wire gt1_rxbufreset_in
.gt1_rxbufstatus_out (), // output wire [2:0] gt1_rxbufstatus_out
.gt1_rxstatus_out (), // output wire [2:0] gt1_rxstatus_out
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
.gt1_rxbyteisaligned_out (), // output wire gt1_rxbyteisaligned_out
.gt1_rxbyterealign_out (), // output wire gt1_rxbyterealign_out
.gt1_rxcommadet_out (), // output wire gt1_rxcommadet_out
.gt1_rxpcommaalignen_in (rxencommaalign_out), // input wire gt1_rxpcommaalignen_in
//------------------- Receive Ports - RX Equalizer Ports -------------------
.gt1_rxdfelpmreset_in (core_reset), // input wire gt1_rxdfelpmreset_in
.gt1_rxmonitorout_out (), // output wire [6:0] gt1_rxmonitorout_out
.gt1_rxmonitorsel_in (), // input wire [1:0] gt1_rxmonitorsel_in
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.gt1_rxoutclkfabric_out (), // output wire gt1_rxoutclkfabric_out
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gt1_gtrxreset_in (core_reset), // input wire gt1_gtrxreset_in
.gt1_rxpcsreset_in (core_reset), // input wire gt1_rxpcsreset_in
.gt1_rxpmareset_in (core_reset), // input wire gt1_rxpmareset_in
//---------------- Receive Ports - RX Margin Analysis ports ----------------
.gt1_rxlpmen_in (1'b1), // input wire gt1_rxlpmen_in
//--------------- Receive Ports - RX Polarity Control Ports ----------------
.gt1_rxpolarity_in (), // input wire gt1_rxpolarity_in
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
.gt1_rxchariscomma_out (), // output wire [3:0] gt1_rxchariscomma_out
.gt1_rxcharisk_out (gt1_rx_rxcharisk), // output wire [3:0] gt1_rxcharisk_out
//---------------------- Receive Ports -RX AFE Ports -----------------------
.gt1_gthrxp_in (rxp[1]), // input wire gt1_gthrxp_in
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.gt1_rxresetdone_out (rx_reset_done1), // output wire gt1_rxresetdone_out
//------------------- TX Initialization and Reset Ports --------------------
.gt1_gttxreset_in (1'b1), // input wire gt1_gttxreset_in
//-------------------- Transmit Ports - TX Buffer Ports --------------------
.gt1_txbufstatus_out (), // output wire [1:0] gt1_txbufstatus_out
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.gt1_txpcsreset_in (), // input wire gt1_txpcsreset_in
//____________________________COMMON PORTS________________________________
.gt0_qplllock_out(),
.gt0_qpllrefclklost_out(),
.gt0_qpllreset_out(),
.gt0_qplloutclk_out(),
.gt0_qplloutrefclk_out(),
.sysclk_in(clk100)
);