Obtenga una copia del último SystemVerilog (supperset of Verilog) LRM. Disponible desde IEEE .
Lea la sección 7.4 "Arreglos empaquetados y desempaquetados". Preste especial atención a las secciones 7.4.4 y 7.4.5.
A continuación se muestra el código de ejemplo:
parameter P = 6:0;
parameter U = 7:0;
// {[packed_range]} name {[unpacked_range]};
reg [P] array [U]; // U unpacked of packed sized P
reg [1:0] [P] array2; // 1:0 packed of packed size P
reg [0:1] [P] array3; // 0:1 packed of packed size P
initial begin
array[0] = 7'b1100000; // assign the packed portion of unpacked
array[1] = 7'b0101000;
array2[0] = array[0]; array2[1] = array[1];
array3[0] = array[0]; array3[1] = array[1];
// U P
$display("%b",array[0][0]); // prints 0 -- U's entry 0, P's entry 0
$display("%b",array[0][1]); // prints 0 -- U's entry 0, P's entry 1
$display("%b",array[0][3]); // prints 0 -- U's entry 0, P's entry 3
$display("%b",array[1][3]); // prints 1 -- U's entry 1, P's entry 3
$display("%d",array[0][6:4]); // prints 6 -- U's entry 0, P's range 6:4
$display("%d",array[1][6:4]); // prints 2 -- U's entry 1, P's range 6:4
$display("%d",array[1]); // prints 28 -- U's entry 1, P's range 6:0 (implied)
//$display("%d",array[1:0][0]); // ** ILLEGAL
//$display("%d",array); // ** ILLEGAL cannot print unpacked
$display("%b",array2[1][3]); // prints 1 -- [1:0]'s entry 1, P's entry 3
$display("%d",array3[1]); // prints 28 -- [0:1]'s entry 1, P's range 6:0 (implied)
$display("%b",array2); // prints 01010001100000 -- implies {array2[1],array2[0]}
$display("%b",array3); // prints 11000000101000 -- implies {array3[0],array3[1]}
end