Sigo este tutorial: Lattice Diamond Jerarchical Design Bench Tutorial
Sin embargo estoy usando Lattice Diamond ver. 3.4.1, y algunos detalles son diferentes. El problema al que me enfrento es con las funciones "Generar símbolo esquemático" y "Plantilla de banco de pruebas VHDL" que se encuentran en la pestaña "Jerarquía" en el panel izquierdo.
En ambos casos, la generación falla con algo similar al siguiente mensaje:
Generating Test Bench Template...
Starting: "source "F:/machx02/simulation_tutorial/hdle_generate_tbtemplate.tcl""
set parameters done
-- Analyzing VHDL file C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd (VHDL-1481)
-- Restoring VHDL parse-tree ieee.std_logic_1164 from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb (VHDL-1493)
-- Restoring VHDL parse-tree std.standard from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/std/standard.vdb (VHDL-1493)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(28): ERROR: boolean is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(29): ERROR: true is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(30): ERROR: string is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(31): ERROR: string is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(32): ERROR: boolean is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(36): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(37): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(38): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(39): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(42): ERROR: true is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(46): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(47): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(48): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(49): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(52): ERROR: true is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(56): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(57): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(58): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(59): ERROR: std_logic is not declared (VHDL-1241)
-- Sorry, too many errors..
-- Analyzing VHDL file F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd (VHDL-1481)
-- Restoring VHDL parse-tree ieee.std_logic_1164 from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb (VHDL-1493)
-- Restoring VHDL parse-tree std.standard from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/std/standard.vdb (VHDL-1493)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(35): ERROR: integer is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(38): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(39): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(40): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(41): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(42): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(45): ERROR: unit dflipflop_nbit ignored due to previous errors (VHDL-1284)
-- VHDL file F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd ignored due to errors (VHDL-1482)
-- Analyzing VHDL file F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd (VHDL-1481)
-- Restoring VHDL parse-tree ieee.std_logic_1164 from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb (VHDL-1493)
-- Restoring VHDL parse-tree std.standard from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/std/standard.vdb (VHDL-1493)
F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd(33): ERROR: integer is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd(36): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd(37): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd(39): ERROR: unit nbitsatadder ignored due to previous errors (VHDL-1284)
-- VHDL file F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd ignored due to errors (VHDL-1482)
-- Analyzing VHDL file F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd (VHDL-1481)
-- Restoring VHDL parse-tree ieee.std_logic_1164 from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb (VHDL-1493)
-- Restoring VHDL parse-tree std.standard from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/std/standard.vdb (VHDL-1493)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(32): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(33): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(34): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(35): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(36): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(37): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(38): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(40): ERROR: unit top_testbench_tutorial ignored due to previous errors (VHDL-1284)
-- VHDL file F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd ignored due to errors (VHDL-1482)
module top_testbench_tutorial is not found.
ERROR: Failed to generate test fixture template file.
Failed to Generate Test Bench Template.
Si no trato de generar la plantilla del banco de pruebas pero uso el código del tutorial directamente, la simulación funciona bien (iniciando el asistente de simulación). Además, si inicio Synplify puedo generar una vista esquemática.
¿Por qué el compilador se queja de estos tipos (std_logic, etc.)?
Y por qué incluso se compila "machx02.vhdl", no se incluye en ninguna fuente (el proyecto es solo de simulación)
Cualquier ayuda apreciada!