Un sistema PWM general utilizando FPGA [cerrado]

Necesito combinar estos 3 códigos para formar un sistema PWM completo utilizando FPGA. Lo intenté, no hay error, pero el proceso no es sintetizable. Por favor, ayúdame. Gracias.

• Este es el código para FreqDivider200Hz

  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity FreqDivider200Hz is
  port(
  clock   : in STD_LOGIC; -- 50 Mhz
  clear   : in STD_LOGIC;
    freq1 : out STD_LOGIC
  );
  end FreqDivider200Hz;
  
  architecture Behavioral of FreqDivider200Hz is
  signal adjfreq: STD_LOGIC_VECTOR(16 downto 0) := "00000000000000000";
  signal adjclock : std_logic := '0';
  
  begin
  
           freq1 <= adjclock;
  
  countClock: process(clock,clear)
  begin
  if (clear = '1') then
      adjfreq <= "00000000000000000";
  elsif(clock'event and clock = '1') then
      -- Flip a the output once every 125,000 cycles (400Hz)
      -- to give a 200Hz output with 50% duty cycle
      if (adjfreq = "11110100001001000") then  
          adjfreq <= "00000000000000000";
              if adjclock <= '0' then
              adjclock <= '1';
              else adjclock <= '0';
              end if;
          else 
          adjfreq <= adjfreq+1;   
      end if;
     end if;
    end process;
   end Behavioral;
  

• Esto es para el código de FreqDivider400Hz

  enter library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity FreqDivider400Hz is
  port(
  clock   : in STD_LOGIC; -- 50 Mhz
  clear   : in STD_LOGIC;
    freq2 : out STD_LOGIC
  );
  end FreqDivider400Hz;
  
  architecture Behavioral of FreqDivider400Hz is
  signal adjfreq: STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000";
  signal adjclock : std_logic := '0';
  
  begin
  
  freq2 <= adjclock;
  
  countClock: process(clock,clear)
  begin
  if (clear = '1') then
      adjfreq <= "0000000000000000";
  elsif(clock'event and clock = '1') then
      -- Flip a the output once every 62500 cycles
      -- to give a 400Hz output with 50% duty cycle
      if (adjfreq = "1111010000100100") then  
          adjfreq <= "0000000000000000";
              if adjclock <= '0' then
              adjclock <= '1';
              else adjclock <= '0';
              end if;
          else 
          adjfreq <= adjfreq+1;   
     end if;
    end if;
   end process;
  end Behavioral;code here
  

• Este es el código para el multiplexor 2x1

  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  ---- Uncomment the following library declaration if instantiating
  ---- any Xilinx primitives in this code.
  --library UNISIM;
  --use UNISIM.VComponents.all;
  
  entity mux2to1 is
  Port ( freq1 : in  STD_LOGIC;
         freq2 : in  STD_LOGIC;
         sel : in  STD_LOGIC;
         y : out  STD_LOGIC);
  end mux2to1;
  
  architecture mux2to1 of mux2to1 is
  
  begin
  
  p1: process (freq1, freq2, sel)
  begin
  if sel = '0' then
          y <= freq1;
  else
          y <= freq2;
  end if;
  end process p1;
  End mux2to1;
  

• Este es el código para el sistema general

  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity OverallSystem is 
  Port ( clock : in STD_LOGIC; 
           clear : in STD_LOGIC; 
           sel : in STD_LOGIC; 
           y : out STD_LOGIC ); 
  end OverallSystem;
  
  architecture Behavioral of OverallSystem is
  component FreqDivider200Hz is
  port(
       clock   : in STD_LOGIC;
       clear   : in STD_LOGIC;
       freq1 : out STD_LOGIC);
  end component;
  
  component FreqDivider400Hz is
  port(
       clock   : in STD_LOGIC;
       clear   : in STD_LOGIC;
       freq2 : out STD_LOGIC);
  end component;
  
  component mux2to1 is
  Port ( freq1 : in  STD_LOGIC;
         freq2 : in  STD_LOGIC;
         sel : in  STD_LOGIC;
         y : out  STD_LOGIC);
  end component;
  
  signal freq1 : std_logic; 
  signal freq2 : std_logic;
  
  begin
  
  chip1 : mux2to1 port map ( freq1 => freq1, freq2 => freq2, sel => sel, y => y );
  chip2 : FreqDivider200Hz port map ( clock => clock, clear => clear, freq1 => freq1 );
  chip3 : FreqDivider400Hz port map ( clock => clock, clear => clear, freq2 => freq2 ); 
  
  end Behavioral;