VHDL: muestra 4 dígitos en la pantalla de 7 segmentos

Escribí un código vhdl, que mostraría 4 dígitos en las pantallas de 7 segmentos de cpld. Utilicé una máquina de estados para seleccionar la pantalla, y con ... seleccionar instrucciones para seleccionar un conjunto de bits dados a la pantalla actual.

entity disp is
    Port ( clk_in : in  STD_LOGIC;
           an1 : out  STD_LOGIC;
           an2 : out  STD_LOGIC;
           an3 : out  STD_LOGIC;
           an4 : out  STD_LOGIC);
           g : out  STD_LOGIC;
           f : out  STD_LOGIC;
           e : out  STD_LOGIC;
           d : out  STD_LOGIC;
           c : out  STD_LOGIC;
           b : out  STD_LOGIC;
           a : out  STD_LOGIC);
end disp;

architecture Behavioral of disp is
    type states is (s0, s1, s2, s3);
    signal present_state, next_state: states;
    signal outp: std_logic_vector (0 to 3);
    signal counter: integer range 0 to 199999:=0;
    signal tym: std_logic:='0';
    signal clk_out: std_logic;
    signal WY : std_logic_vector (6 downto 0);
    signal WE : std_logic_vector (3 downto 0);

begin

--state machine
process (present_state)
begin   
    case present_state is
        when s0 =>
            outp <= "0111";
            next_state <= s1;                
        when s1 =>
            outp <= "1011";
            next_state <= s2;    
        when s2 =>
            outp <= "1101";
            next_state <= s3;
        when s3 =>
            outp <= "1110";
            next_state <= s0;
    end case;
end process;

--frequency divider
process (clk_in)
begin                       
    if (rising_edge(clk_in)) then
            if (counter = 199999) then
                    tym <= not tym;
                    counter <= 0;
                    else
                    counter <= counter+1;
            end if;
    end if;
end process;

clk_out <= tym;

--state changing
process (clk_out)
begin
    if (rising_edge(clk_out)) then
        present_state <= next_state;
    end if;
end process;

an1<=outp(0);
an2<=outp(1);
an3<=outp(2);
an4<=outp(3);

--set of bits for 7-segment display
WE <= an4 & an3 & an2 & an1;
with WE select
WY <= "1000000" when "0111", --display 0
           "1111001" when "1011", --display 1
           "0100100" when "1101", --display 2
           "0000000" when "1110", --display  8
           "1111111" when others; --display nothing

g <= WY(6);
f <= WY(5);
e <= WY(4);
d <= WY(3);
c <= WY(2);
b <= WY(1);
a <= WY(0);

end Behavioral;

Hago algo incorrecto con la entrada con instrucción ... select, porque Xilinx muestra un error para la línea en negrita que dice "No se puede leer desde 'fuera' del objeto an4; use 'búfer' o 'inout'". ¿Cómo resolver este problema?