¿Cómo fusionar estos dos códigos vhdl?

Estamos intentando diseñar un programa que agregue ruido a la señal sinusoidal. Hemos diseñado un código para generar una señal sinusoidal y hemos encontrado un código para generar ruido. Queremos unir los dos. Verifique si la fusión es correcta en no. (Sabemos que el código no es sintetizable ya que estamos utilizando variables reales)

Después de fusionar el código, se supone que el ruido (DATA_OUTTT) se agrega a la señal sinusoidal (data_out1) y da como resultado (noisy_signal). La cantidad de ruido en cada punto es algo (es decir, menos de 1). Entonces, ¿por qué la señal de ruido agregado (noisy_signal) que muestra valores de ruido de más de 1 se agrega o se resta?

¿Es posible que esta parte del código se haya agregado de forma incorrecta ?:

for i in 0 to nn-1 loop    -- nn noise generators
                   UNIFORM (s1(i),s2(i),r(i));
                   s:=s+r(i);
        end loop;

Estoyincluyendolostrescódigos:

1)Elcódigoparagenerarsinusoide:

libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.NUMERIC_STD.ALL;--trytousethislibraryasmuchaspossible.entitysine_waveisport(clk:instd_logic;data_out:outSTD_LOGIC_VECTOR(7downto0));endsine_wave;architectureBehavioralofsine_waveissignali:integerrange0to29:=0;--typememory_typeisarray(0to29)ofinteger;typememory_typeisarray(0to29)ofstd_logic_vector(7downto0);--ROMforstoringthesinevaluesgeneratedbyMATLAB.signalsine:memory_type:=("01001101","01011101","01101100","01111010","10000111","10010000","10010111","10011010","10011010","10010111","10010000","10000111","01111010","01101100","01011101","01001101",
"00111101","00101110","00100000","00010011","00001010","00000011","00000000","00000000","00000011","00001010","00010011","00100000","00101110","00111101");
--hi
begin

process(clk)
begin
  --to check the rising edge of the clock signal
if(rising_edge(clk)) then     
data_out <= sine(i);
i <= i+ 1;
if(i = 29) then
i <= 0;
end if;
end if;
end process;

end Behavioral;

2) Código para generar ruido:

library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.math_real.all;
 entity Gauss_Gen is
  generic(nn:natural:=1; --power of the binomial distribution <16
  m:REAL:=0.0    -- mean output value
    );
   port(
    CLK : in STD_LOGIC;
    RST : in STD_LOGIC;
    DATA_OUT : out REAL:=0.0
    );
   end Gauss_Gen;
 architecture Model of Gauss_Gen is
        type arri is array (0 to 15) of integer;
        type arrr is array (0 to 15) of real;
 begin
 SFR:process(clk,rst)
  variable s1:arri:=(3,33,333,3,4,5,6,7,8,9,11,22,33,others=>55);
  variable s2:arri:=(5,55,555,50,6,7,8,9,5,6,7,21,33,others=>22);
  variable r:arrr:=(others=>0.0);
  variable s:real:=0.0;
        begin
           if rst='1' then
              DATA_OUT<=0.0;
           elsif  clk='1' and clk'event then
        s:=0.0;
        for i in 0 to nn-1 loop    -- nn noise generators
                   UNIFORM (s1(i),s2(i),r(i));
                   s:=s+r(i);
        end loop;
            DATA_OUT <= 2.0*(s/real(nn)-0.5)+ m;
           end if;
      end process;
  end Model;

3) El código combinado:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;  --try to use this library as much as possible.
 use IEEE.math_real.all;


entity sine_wave is

 generic(nn:natural:=1; --power of the binomial distribution <16
   m:REAL:=0.0     -- mean output value
     );

port (clk :in  std_logic;
      data_out : out STD_LOGIC_VECTOR(7 downto 0);
      DATA_OUTT : out REAL:=0.0
      );
end sine_wave;

architecture Behavioral of sine_wave is

type arri is array (0 to 15) of integer;
type arrr is array (0 to 15) of real;

signal data_out1 :  STD_LOGIC_VECTOR(7 downto 0);
signal  noisy_signal,DATA_OUTTT : real;
signal i : integer range 0 to 29:=0;
--type memory_type is array (0 to 29) of integer;
type memory_type is array (0 to 29) of std_logic_vector(7 downto 0); 
--ROM for storing the sine values generated by MATLAB.
signal sine : memory_type :=("01001101","01011101","01101100","01111010","10000111","10010000","10010111","10011010","10011010","10010111","10010000","10000111","01111010","01101100","01011101","01001101",
"00111101","00101110","00100000","00010011","00001010","00000011","00000000","00000000","00000011","00001010","00010011","00100000","00101110","00111101");
--hi
begin

process(clk)
 variable s1:arri:=(3,33,333,3,4,5,6,7,8,9,11,22,33,others=>55);
 variable s2:arri:=(5,55,555,50,6,7,8,9,5,6,7,21,33,others=>22);
 variable r:arrr:=(others=>0.0);
 variable s:real:=0.0;
begin
  --to check the rising edge of the clock signal
if(rising_edge(clk)) then 

s:=0.0;
        for i in 0 to nn-1 loop    -- nn noise generators
                   UNIFORM (s1(i),s2(i),r(i));
                   s:=s+r(i);
        end loop;
            DATA_OUTT <= 2.0*(s/real(nn)-0.5)+ m;
            DATA_OUTTT <= 2.0*(s/real(nn)-0.5)+ m; 

data_out <= sine(i);
data_out1 <= sine(i);
noisy_signal<=real(to_integer(unsigned(data_out1)))+DATA_OUTTT;
i <= i+ 1;
if(i = 29) then
i <= 0;
end if;
end if;
end process;

end Behavioral;