La simulación en VHDL falla

Soy un novato en Vivado y estoy tratando de escribir un banco de pruebas para hacer una simulación. Estoy tratando de hacer el banco de pruebas para este componente.

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity branchcontrol is
    Port ( PL : in STD_LOGIC;
           BC : in STD_LOGIC_VECTOR(3 downto 0);
           PC : in STD_LOGIC_VECTOR (31 downto 0);
           AD : in STD_LOGIC_VECTOR (31 downto 0);
           Flags : in STD_LOGIC_VECTOR(3 downto 0);
           PCLoad : out STD_LOGIC;
           PCValue : out STD_LOGIC_VECTOR (31 downto 0));
end branchcontrol;

architecture Behavioral of branchcontrol is

signal Z,N,P,C,V: std_logic;

begin

Z <= Flags(3);        -- zero flag
N <= Flags(2);        -- negative flag
P <= not N and not Z; -- positive flag
C <= FLags(1);        -- carry flag
V <= Flags(0);        -- overflow flag


PCLoad <= PL and not(BC(3)) and ((not (BC(2)) and not (BC(1))) or ((not Z and BC(0)) and (BC(1) xnor N)) or (not BC(2) and(BC(0) xor Z)));

PCValue<=PC+AD;

end Behavioral;

Y mi banco de pruebas

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity testBranchControl is
end testBranchControl;

architecture Behavioral of testBranchControl is

component branchcontrol
    Port ( 
           PL : in STD_LOGIC;
           BC : in STD_LOGIC_VECTOR(3 downto 0);
           PC : in STD_LOGIC_VECTOR (31 downto 0);
           AD : in STD_LOGIC_VECTOR (31 downto 0);
           Flags : in STD_LOGIC_VECTOR(3 downto 0);
           PCLoad : out STD_LOGIC;
           PCValue : out STD_LOGIC_VECTOR (31 downto 0)
           );
end component;


signal PL, PCLoad: std_logic:='0'; 
signal BC, Flags: std_logic_vector(3 downto 0):="0000"; 
signal PC, AD, PCValue: std_logic_vector(31 downto 0):=(31 downto 0 => '0'); 

begin

    test_unit: branchcontrol port map(
         PL => PL, BC => BC, PC => PC, AD => AD,
         Flags => Flags, PCLoad => PCLoad,
         PC => PCValue); 

         process begin
            wait for 30 ns; 
            PL <= '0'; BC<="0000"; Flags<="0000"; AD<=x"00000101"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0000"; Flags<="0000"; AD<=x"00000101"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0010"; Flags<="1000"; AD<=x"00001100"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0010"; Flags<="0000"; AD<=x"00000101"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0011"; Flags<="1000"; AD<=x"00000101"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0011"; Flags<="0000"; AD<=x"00000001"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0100"; Flags<="0000"; AD<=x"00001001"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0100"; Flags<="0100"; AD<=x"00001001"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0100"; Flags<="1000"; AD<=x"00001001"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0100"; Flags<="1100"; AD<=x"00001001"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0101"; Flags<="0000"; AD<=x"00000110"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0101"; Flags<="0100"; AD<=x"00001110"; 
            wait for 30 ns;    
            PC<=PCValue; PL <= '1'; BC<="0101"; Flags<="1000"; AD<=x"00001110"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0101"; Flags<="1100"; AD<=x"00000000"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0110"; Flags<="0000"; AD<=x"00000000"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0110"; Flags<="0100"; AD<=x"00000000"; 
            wait for 30 ns;     
            PC<=PCValue; PL <= '1'; BC<="0110"; Flags<="1000"; AD<=x"0000F0F0"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0110"; Flags<="1100"; AD<=x"0000F0F0"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0111"; Flags<="0000"; AD<=x"0000F0F0"; 
            wait for 30 ns;      
            PC<=PCValue; PL <= '1'; BC<="0111"; Flags<="0100"; AD<=x"0000F0F0"; 
            wait for 30 ns;
            PC<=PCValue; PL <= '1'; BC<="0111"; Flags<="1000"; AD<=x"0000AB00"; 
            wait for 30 ns;              
            PC<=PCValue; PL <= '1'; BC<="0111"; Flags<="1100"; AD<=x"0000AB00"; 
            wait for 30 ns;                                                     
            wait;
         end process;


end Behavioral;

El Vivado simplemente dice que el paso de compilación falló con errores y que se detectó un error al ejecutar la simulación. También estoy usando la versión 2016.3 de Vivado si eso ayuda. Estoy realmente atrapado en esto y no puedo ver mi error.

¿Puede alguien ayudarme por favor? Gracias.