Tipo de destino std.standard.bit en la asignación de variables es diferente de std_logic_1164.std_ulogic?

Lo siento si el formato no es bueno pero soy nuevo con eso .. Estoy intentando seleccionar un bit de una señal sin firmar para que se asigne a una variable de bit, ¡¡pero no funciona !! He intentado asignarlo en un proceso pero no funciona también Aparecen los siguientes errores

** Error: D:/Electronic Engineering Faculty/FeeSparc/The_very_last source_code/cache_mem/cache_mem.vhd(70): Target type std.standard.bit in variable assignment is different from expression type ieee.std_logic_1164.std_ulogic.
** Error: D:/Electronic Engineering Faculty/FeeSparc/The_very_last source_code/cache_mem/cache_mem.vhd(71): Target type std.standard.bit in variable assignment is different from expression type ieee.std_logic_1164.std_ulogic.
** Error: D:/Electronic Engineering Faculty/FeeSparc/The_very_last source_code/cache_mem/cache_mem.vhd(114): VHDL Compiler exiting

¿Alguna ayuda con eso por favor?

--Cache design
--2 sets, 2 ways, block size=4 words
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;

entity cache_mem is port (
c_add : in unsigned(31 downto 0);
c_d_in : in unsigned(31 downto 0);
c_clk : in bit;
c_wen : in bit; 
c_d_out : out unsigned(31 downto 0);
c_hit : out bit;
c_dirty : out bit;
finish : out bit);
end cache_mem;

architecture arc_cache_mem of cache_mem is
type cache_type is array(79 downto 0) of unsigned(31 downto 0);
signal cache : cache_type;
signal set,sel : integer range 0 to 1000;
signal hit_0,hit_1:bit; 

begin 
--set 0 
  --block 0
cache(0)<=x"00000000";
cache(1)<=x"00000001";
cache(2)<=x"00000002";
cache(3)<=x"00000003";
cache(4)<=x"01000000";
  --block 1
cache(5)<=x"00000005";
cache(6)<=x"00000006";
cache(7)<=x"00000007";
cache(8)<=x"00000008";
cache(9)<=x"01000001";

  --set 1
    --block 0
cache(10)<=x"00000010";
cache(11)<=x"00000011";
cache(12)<=x"00000012";
cache(13)<=x"00000013";
cache(14)<=x"01000002";
  --block 1
cache(15)<=x"00000015";
cache(16)<=x"00000016";
cache(17)<=x"00000017";
cache(18)<=x"00000018";
cache(19)<=x"01000003";




set<=conv_integer(c_add(7 downto 4))*10;
sel<=conv_integer(c_add(3 downto 2));



process(c_clk)
variable dirty_0,dirty_1:bit;  
variable temp_0,temp_1: unsigned (31 downto 0);  
--variable out_0,out_1:unsigned (31 downto 0);
begin
temp_0:=cache(set+4);
temp_1:=cache(set+9);

----HERE IS THE ERROR----

dirty_0:=temp_0(25);
dirty_1:=temp_1(25);


 if(c_add(31 downto 8)=temp_0(23 downto 0) and temp_0(24)='1') then 
   hit_0<='1';
--   case sel is 
--    when 0 => out_0<=cache(set);
--    when 1 => out_0<=cache(set+1);
--    when 2 => out_0<=cache(set+2);
--    when others => out_0<=cache(set+3); 
--  end case;

elsif(c_add(31 downto 8)/=temp_0(23 downto 0) or temp_0(24)='0') then 
  hit_0<='0';
end if;  

if(c_add(31 downto 8)=temp_1(23 downto 0) and temp_1(24)='1') then 
  hit_1<='1';
--    case sel is 
--    when 0 => out_1<=cache(set+5);
--    when 1 => out_1<=cache(set+6);
--    when 2 => out_1<=cache(set+7);
--    when others => out_1<=cache(set+8); 
--    end case;

elsif(c_add(31 downto 8)/=temp_1(23 downto 0) or temp_1(24)='0') then 
  hit_1<='0';
end if; 

if(hit_0='1') then 
--  cache_out<=out_0;
  c_hit<='1';
  c_dirty<=dirty_0;
elsif(hit_1='1') then 
--  cache_out<=out_1;
  c_hit<='1';
  c_dirty<=dirty_1;
else
  c_hit<='0';
  c_dirty<=dirty_0 or dirty_1;
end if;

end process;
end arc_cache_mem;