Estoy trabajando en un código de diseño de luces traseras para automóviles T-bird, aquí está mi diseño: B significa freno, todas las luces encendidas en el descanso, cuando gire a la izquierda las luces en secuencia: 000000 - > 001000 - > 011000- > 111000 encienda las luces de la derecha en la secuencia: 000000 - > 000001 - > 000011- > 000111
moduletaillight(clka,clkb,restart,brake,right,left,lc,lb,la,ra,rb,rc,state);inputclka,clkb,restart,brake,right,left;outputlc,lb,la,ra,rb,rc;output[2:0]state;wireclka,clkb,restart,brake,right,left;reglc,lb,la,ra,rb,rc;parameterSIZE=3;parameterIDLE=3'b000,l1=3'b001,l2=3'b011,l3=3'b010,B=3'b100,r1=3'b101,r2=3'b111,r3=3'b110;//internalvariablereg[SIZE-1:0]state;//SeqpartoftheFSMwire[SIZE-1:0]c_state;//Internalstateregreg[SIZE-1:0]n_state;//combopartofFSMassignc_state=fsm_function(state,brake,right,left,restart);//----------FunctionforComboLogic-----------------function[SIZE-1:0]fsm_function;input[SIZE-1:0]state,brake,right,left,restart;case(state)IDLE:beginif(!restart&&!brake&&!right&&!left)beginfsm_function=IDLE;endelseif(!restart&&!brake&&!right&&left)beginfsm_function=l1;endelseif(!restart&&!brake&&right&&!left)beginfsm_function=r1;endelseif(!restart&&(brake||(right&&left)))beginfsm_function=B;endendl1:beginif(!brake)beginfsm_function=l2;endelsebeginfsm_function=B;endendl2:beginif(!brake)beginfsm_function=l3;endelsebeginfsm_function=B;endendl3:beginif(!brake)beginfsm_function=IDLE;endelsebeginfsm_function=B;endendr1:beginif(!brake)beginfsm_function=r2;endelsebeginfsm_function=B;endendr2:beginif(!brake)beginfsm_function=r3;endelsebeginfsm_function=B;endendr3:beginif(!brake)beginfsm_function=IDLE;endelsebeginfsm_function=B;endendB:beginfsm_function=IDLE;enddefault:fsm_function=IDLE;endcaseendfunction//----------SeqLogic-----------------------------always@(posedgeclka)begin:FSM_SEQif(restart==1'b1)beginn_state<=IDLE;endelsebeginn_state<=c_state;endend//----------OutputLogic——————————————always@(posedgeclkb)begin:OUTPUT_LOGICcase(n_state)IDLE:beginstate<=n_state;{lc,lb,la,ra,rb,rc}<=6'b000000;endl1:beginstate<=n_state;{lc,lb,la,ra,rb,rc}<=6'b001000;endl2:beginstate<=n_state;{lc,lb,la,ra,rb,rc}<=6'b011000;endl3:beginstate<=n_state;{lc,lb,la,ra,rb,rc}<=6'b111000;endr1:beginstate<=n_state;{lc,lb,la,ra,rb,rc}<=6'b000001;endr2:beginstate<=n_state;{lc,lb,la,ra,rb,rc}<=6'b000011;endr3:beginstate<=n_state;{lc,lb,la,ra,rb,rc}<=6'b000111;endB:beginstate<=n_state;{lc,lb,la,ra,rb,rc}<=6'b111111;endendcaseend//EndOfBlockOUTPUT_LOGICendmodule//EndofModuletwoP_FSMmibancodepruebasescomo:
moduletaillight_tb();regin_clka,in_clkb,in_restart,in_brake,in_right,in_left;wireout_lc,out_lb,out_la,out_ra,out_rb,out_rc;wire[2:0]out_state;integeri;parameter[5:0]value=6'b000000;//createanFSMinstance.taillightU1(.clka(in_clka),.clkb(in_clkb),.restart(in_restart),.brake(in_brake),.right(in_right),.left(in_left),.lc(out_lc),.lb(out_lb),.la(out_la),.rc(out_rc),.rb(out_rb),.ra(out_ra),.state(out_state));initialbeginfor(i=0;i<64;i=i+1)begin{in_clka,in_clkb,in_restart,in_brake,in_right,in_left}=value+i;#1;end$dumpfile("taillight_tb.vcd");
$dumpvars;
$display ("in_clka,\t in_clkb,\t in_restart,\t in_brake, \t in_right, \t in_left \t out_lc, \t out_lb, \t out$
$stop;
end
endmodule
Pero cuando pruebo mi código en moldesim, la forma de onda se ve así:
