generador de secuencia PN usando un registro de desplazamiento de realimentación lineal en VHDL

Obtuve un código para el generador de secuencia PN que usa el registro de desplazamiento de retroalimentación lineal en VHDL.

Estoy usando 1010 como semilla inicial, pero en la salida, las cuatro secuencias PN son 1 .

¿Qué cambios debo hacer para obtener diferentes secuencias de PN?

Estoy usando Xilinx ISE 10.1. Este es el código.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity pnsmall_1 is
  Port (
    clock           : in  STD_LOGIC;                    -- synchronous clock input
    init            : in  STD_LOGIC_vector (3 downto 0);    -- the seed
    pn1,pn2,pn3,pn4 : out STD_LOGIC);                   -- PN sequence
end pnsmall_1;

architecture Behavioral of pnsmall_1 is
  component dp
    port (
      clk,clr,pst,d : in  std_logic;
      q             : out std_logic
    );
  end component;

  component exor
    port (
      a,b : in  std_logic;
      z   : out std_logic
    );
  end component;

  signal q0          : std_logic;   -- 1st stage out
  signal q1          : std_logic;   -- 2nd stage out
  signal q2          : std_logic;   -- 3th stage out
  signal q3          : std_logic;   -- 4th stage out
  signal x           : std_logic;   -- 1st stage input, the feedback
  signal qout        : std_logic_vector(7 downto 0);

begin
  s0: dp port map(
        clk => clock,
        clr => '0',
        pst => init(0),
        d   => x,
        q   => q0
        );
  s1: dp port map(
        clk => clock,
        clr => '0',
        pst => init(1),
        d   => q0,
        q   => q1
        );
  s2: dp port map(
        clk => clock,
        clr => '0',
        pst => init(2),
        d   => q1,
        q   => q2
        );
  s3: dp port map(
        clk => clock,
        clr => '0',
        pst => init(3),
        d   => q2,
        q   => q3
        );

  xx: exor port map(q0,q3,x);

  process(clock)
  begin
    qout(0)<=q3;
    if(clock'event and clock='1') then
      for i in 0 to 6 loop
        qout(i+1)<=qout(i);
      end loop;

      pn1<=qout(1);
      pn2<=qout(3);
      pn3<=qout(5);
      pn4<=qout(7);
    end if;
  end process;
end Behavioral;

el código para dp está debajo

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM; 
use UNISIM.VComponents.all;

-- Code for D FlipFlop with synchronous clear and preset.
entity dp is
   Port (
       clk : in STD_LOGIC; -- synchronous clock
       clr : in STD_LOGIC; -- clear
       pst : in STD_LOGIC; -- preset
       d   : in STD_LOGIC; -- data input
       q   : out STD_LOGIC -- data output
       );
end dp;

architecture Behavioral of dp is
begin
    process(clk,pst,clr) 
      begin 
        if(pst='1')then 
            q<='1';
          elsif(clr='1')then
            q<='0'; 
          elsif (clk'event and clk='1') then 
            q<=d;
        end if;
    end process; 
end Behavioral;