En SystemVerilog me encantaría crear instancias de módulos como
const int primeArray [11] = '{3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37};
logic clock, reset, increment;
logic [10:0] match;
generate
genvar n;
for (n = 0; n < 11; n++)
begin
PrimeCounter #(primeArray[n]) counter (.clock, .reset, .increment, .match(match[n]));
end
endgenerate
Desafortunadamente, primeArray [n] no se puede pasar como parámetro, ya que aparentemente no es realmente constante. ¿Hay alguna manera de lograr esto? ¿O estoy atorado de instancia
PrimeCounter #(3) counter0(.clock, .reset, .increment, .match(match[0]));
PrimeCounter #(5) counter1(.clock, .reset, .increment, .match(match[1]));
PrimeCounter #(7) counter2(.clock, .reset, .increment, .match(match[2]));
PrimeCounter #(11) counter3(.clock, .reset, .increment, .match(match[3]));
PrimeCounter #(13) counter4(.clock, .reset, .increment, .match(match[4]));
PrimeCounter #(17) counter5(.clock, .reset, .increment, .match(match[5]));
PrimeCounter #(19) counter6(.clock, .reset, .increment, .match(match[6]));
PrimeCounter #(23) counter7(.clock, .reset, .increment, .match(match[7]));
PrimeCounter #(29) counter8(.clock, .reset, .increment, .match(match[8]));
PrimeCounter #(31) counter9(.clock, .reset, .increment, .match(match[9]));
PrimeCounter #(37) counter10(.clock, .reset, .increment, .match(match[10]));
?