Verilog: Cómo evitar 'Redeclaración de puerto ansi'

Estoy intentando implementar una condición de inicio para i2c. Y a la simulación ISim lo hice. Sin embargo, sigo recibiendo esta advertencia:

WARNING:HDLCompiler:751 - "timer_A.v" Line 40: Redeclaration of ansi port flags_timer_A is not allowed
WARNING:HDLCompiler:751 - "start_i2c.v" Line 31: Redeclaration of ansi port rst_to_tmr is not allowed
WARNING:HDLCompiler:751 - "start_i2c.v" Line 35: Redeclaration of ansi port start_done is not allowed

Estoy confundido porque creo que solo declaré reg flags_timer_A en el módulo timer_A y solo declaré regs rst_to_tmr y start_done en el módulo start_i2c. También las simulaciones muestran que funciona, pero ¿por qué sigo recibiendo las advertencias? ¿Estoy haciendo algo que no está bien? Si es así, ¿qué es? Gracias.

Este es el módulo timer_A:

module timer_A(
    input clk,   // which clock?
    input rst,   // sets to 0 or up counter
    //output [7:0] flags_timer_A,   // sets flag when counts to the value
    input mode,   // if mode 0, counts up to A only flags A, if 1 counts to
                        // A and B, C, D ... flags if they are not 0.
    input [15:0] count_to_A,  // counts to first value
    input [15:0] count_to_B,  // counts to second value
    input count_to_C,
    input count_to_D,
    input count_to_E,
    input count_to_F,
    input count_to_G,
    input count_to_H,
    output [7:0] flags_timer_A
);

reg [15:0] timer_A_Reg;

reg [7:0] flags_timer_A;

/*
timer_A_flag_A  = flags_timer_A[0]

timer_A_flag_B  = flags_timer_A[1]

timer_A_flag_C  = flags_timer_A[2]

timer_A_flag_D  = flags_timer_A[3] ...
*/


always @(posedge rst) begin
    flags_timer_A = 8'b0;
    timer_A_Reg = 16'b0;
end

always @(posedge clk) begin
    if (rst) begin
        flags_timer_A = 8'b0;
        timer_A_Reg = 16'b0;
    end
    else if (!rst) begin
        if (mode == 1'b0) begin
            if (timer_A_Reg != count_to_A) begin
                timer_A_Reg <= timer_A_Reg + 1;
            end
            else begin
                flags_timer_A[0] <= 1'b1;
            end
        end
        else begin
            if (timer_A_Reg != count_to_A) begin
                timer_A_Reg = timer_A_Reg + 1;
                if (timer_A_Reg == count_to_B) begin
                    flags_timer_A[1] = 1'b1;
                end
                else if (timer_A_Reg == count_to_C) begin
                    flags_timer_A[2] = 1'b1;
                end
                else if (timer_A_Reg == count_to_D) begin
                    flags_timer_A[3] = 1'b1;
                end
                else if (timer_A_Reg == count_to_E) begin
                    flags_timer_A[4] = 1'b1;
                end
                else if (timer_A_Reg == count_to_F) begin
                    flags_timer_A[5] = 1'b1;
                end
                else if (timer_A_Reg == count_to_G) begin
                    flags_timer_A[6] = 1'b1;
                end
                else if (timer_A_Reg == count_to_H) begin
                    flags_timer_A[7] = 1'b1;
                end
            end
            else begin
                flags_timer_A[0] <= 1'b1;
            end
        end
    end
end


endmodule

Este es el módulo start_i2c:

'include "timer_A.v"
module start_i2c(
        input start,
        input [7:0] flags_timer_A,
        input clk,
        output rst_to_tmr,
        output start_done
);

reg [0:0] resetter_flag;
reg [0:0] rst_to_tmr;
reg [0:0] scl;
reg [0:0] sda;
reg [0:0] mode_to_tmr;
reg [0:0] start_done;
/*
timer_A_flag_A  = flags[0]

timer_A_flag_B  = flags[1]

timer_A_flag_C  = flags[2]

timer_A_flag_D  = flags[3] ...
*/

always @(posedge start) begin
    resetter_flag <= 1'b0;
    mode_to_tmr <= 1'b1;
    start_done <= 1'b0;
    scl <= 1'b1;
    sda <= 1'b1;
end

parameter min_SDA_on_time = 0;  
parameter min_SDA_SCL_fall_delay = 0;

always @(negedge clk)
begin: RESETTER    // this resets up when start is on immediately
    if (start && !resetter_flag) begin
        rst_to_tmr = 1'b1;
        resetter_flag = 1'b1;
    end
    else if (start && resetter_flag) begin
        rst_to_tmr <= 1'b0;
    end
end

always @(posedge clk) begin
    if (start) begin
        if (flags_timer_A[1]) begin
            sda <= 1'b0;
        end
        if (flags_timer_A[0]) begin
            scl <= 1'b0;
            start_done <= 1'b1;
        end
    end
    else begin

    end
end

always @(negedge start) begin
    resetter_flag = 1'b0;
    start_done <= 1'b0;
end

timer_A  start_timer(
    .clk             (clk),   // which clock?
    .rst             (rst_to_tmr),   // sets to 0 or up counter
    .mode     (mode_to_tmr),   // if mode 0, counts up to A only flags A, if 1 counts to
                                        // A and B, C, D ... flags if they are not 0.
    .count_to_A      (min_SDA_on_time + min_SDA_SCL_fall_delay),  // counts to first value
    .count_to_B      (min_SDA_on_time),  // counts to second value
    .count_to_C      (16'b0),
    .count_to_D      (16'b0),
    .count_to_E      (16'b0),
    .count_to_F      (16'b0),
    .count_to_G      (16'b0),
    .count_to_H      (16'b0),
    .flags_timer_A   (flags_timer_A)  // sets flag when counts to the value
);

endmodule

y este es el módulo de prueba:

'include "start_i2c.v"
module start_i2c_tb(
    );

//defparam start_test.min_SDA_on_time = 16'b11001000;

//defparam start_test.min_SDA_SCL_fall_delay = 16'b01100100; 

reg [0:0] start;

wire [7:0] flags_timer_A;

reg [0:0] clk;

initial begin

    clk = 1'b0;
    start = 1'b0;
    #5 start = 1'b1;
    #40000 $finish;

end

always begin
    #1 clk = ~ clk;
end

start_i2c #(16'b11001000, 16'b01100100) start_test(
        .start          (start),
        .flags_timer_A  (flags_timer_A),
        .clk            (clk),
        .rst_to_tmr     (rst_to_tmr),
        .start_done     (start_done)
);

endmodule