Problema al conectar el divisor de reloj generado por CORE Generator al diseño I2S para Spartan 6

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Estoy tratando de conectar el divisor de reloj generado por el Generador CORE al receptor I2S y al transmisor I2S en Spartan 6. La PLL_BASE se conecta a través del módulo ODDR2, según se recomienda. Tanto el receptor como el transmisor funcionan cuando los relojes se dividen sin bloqueos desde CORE Generator.

Código

clk_wiz_v3_6.vhd 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

entity clk_wiz_v3_6 is
port
 (-- Clock in ports
  CLK_IN1           : in     std_logic;
  -- Clock out ports
  mclk          : out    std_logic;
  sclk          : out    std_logic;  
  -- Status and control signals
  RESET         : in     std_logic
 );
end clk_wiz_v3_6;

architecture xilinx of clk_wiz_v3_6 is
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
  -- Input clock buffering / unused connectors
  signal clkin1      : std_logic;
  -- Output clock buffering / unused connectors
  signal clkfbout         : std_logic;
  signal clkout0          : std_logic;
  signal clkout1          : std_logic;
  signal clkout2_unused   : std_logic;
  signal clkout3_unused   : std_logic;
  signal clkout4_unused   : std_logic;
  signal clkout5_unused   : std_logic;
  -- Unused status signals
  signal locked_unused    : std_logic;

  signal clk0obuf : std_logic;
  signal clk0bufg : std_logic;
  signal notclk0bufg : std_logic;
  signal clk1bufg : std_logic;
  signal notclk1bufg : std_logic;
  signal clk1obuf : std_logic;

begin

    notclk0bufg <= clk0bufg;
    notclk1bufg <= clk1bufg;

  -- Input buffering
  --------------------------------------
  clkin1_buf : IBUFG
  port map
   (O => clkin1,
    I => CLK_IN1);


  -- Clocking primitive
  --------------------------------------
  -- Instantiation of the PLL primitive
  --    * Unused inputs are tied off
  --    * Unused outputs are labeled unused

  pll_base_inst : PLL_BASE
  generic map
   (BANDWIDTH            => "OPTIMIZED",
    CLK_FEEDBACK         => "CLKFBOUT",
    COMPENSATION         => "INTERNAL",
    DIVCLK_DIVIDE        => 4,
    CLKFBOUT_MULT        => 29,
    CLKFBOUT_PHASE       => 0.000,
    CLKOUT0_DIVIDE       => 59,
    CLKOUT0_PHASE        => 0.000,
    CLKOUT0_DUTY_CYCLE   => 0.500,
    CLKOUT1_DIVIDE       => 118,
    CLKOUT1_PHASE        => 0.000,
    CLKOUT1_DUTY_CYCLE   => 0.500,
    CLKIN_PERIOD         => 10.000,
    REF_JITTER           => 0.010)
  port map
    -- Output clocks
   (CLKFBOUT            => clkfbout,
    CLKOUT0             => clkout0,
    CLKOUT1             => clkout1,
    CLKOUT2             => clkout2_unused,
    CLKOUT3             => clkout3_unused,
    CLKOUT4             => clkout4_unused,
    CLKOUT5             => clkout5_unused,
    -- Status and control signals
    LOCKED              => locked_unused,
    RST                 => RESET,
    -- Input clock control
    CLKFBIN             => clkfbout,
    CLKIN               => clkin1);

       ODDR2_inst : ODDR2
   generic map(
      DDR_ALIGNMENT => "NONE",
      INIT => '0',
      SRTYPE => "SYNC")
   port map (
      Q => clk0obuf,    -- 1-bit output data
      C0 => clk0bufg,       -- 1-bit clock input
      C1 => NOTclk0bufg, -- 1-bit clock input
      CE => '1',              -- 1-bit clock enable input
      D0 => '1',
      D1 => '0',
      R => '0',    -- 1-bit reset input
      S => '0'     -- 1-bit set input
   );

      ODDR2_inst2 : ODDR2
   generic map(
      DDR_ALIGNMENT => "NONE",
      INIT => '0',
      SRTYPE => "SYNC")
   port map (
      Q => clk1obuf,    -- 1-bit output data
      C0 => clk1bufg,       -- 1-bit clock input
      C1 => NOTclk1bufg, -- 1-bit clock input
      CE => '1',              -- 1-bit clock enable input
      D0 => '1',
      D1 => '0',
      R => '0',    -- 1-bit reset input
      S => '0'     -- 1-bit set input
   );

  -- Output buffering
  -------------------------------------


  clkout1_buf : BUFG
  port map
   (O   => clk0bufg, --mclk
    I   => clkout0);

  clkout2_buf : BUFG
  port map
   (O   => clk1bufg, --sclk
    I   => clkout1);

    clkout3_buf : OBUF
    port map
    (O   => mclk, --mclk
     I   => clk0obuf);

    clkout4_buf : OBUF
    port map
    (O   => sclk, --sclk
    I   => clk1obuf);

end xilinx;

i2sClocks.vhd 

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity i2sClocks is
    port
     (
        clk     : in std_logic;
        lrclk   : out std_logic
    );
end i2sClocks;

architecture rtl of i2sClocks is

    signal i2sClocksDivider_i :std_logic_vector(6 downto 0) := (others => '0');

begin

    lrclk <= i2sClocksDivider_i(6);

   process(clk)
   begin
        if rising_edge(clk) then
            i2sClocksDivider_i <= std_logic_vector(unsigned(i2sClocksDivider_i) + 1);
      end if;
    end process;

end rtl;

receiver.vhd 

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity i2sReceiver is
    port(
        serialClock : in std_logic;
        wordSelect  : in std_logic;
        serialData  : in std_logic;
        lastSample  : out std_logic_vector(23 downto 0) := (others => '0')
    );
end i2sReceiver;

architecture rtl of i2sReceiver is

    signal currentSample_i : std_logic_vector(23 downto 0) := (others => '0');
    signal currentSampleIndex_i : std_logic_vector(5 downto 0) := (others => '0');   
    signal lastWordSelect_i : std_logic;

begin

    process(serialClock)
    begin
        if rising_edge(serialClock) then    
            currentSampleIndex_i <= std_logic_vector(unsigned(currentSampleIndex_i) + 1);

            if currentSampleIndex_i(4 downto 0) < "11000" then
                currentSample_i(to_integer(unsigned(currentSampleIndex_i(4 downto 0)))) <= serialData;
            end if;

            if (lastWordSelect_i = (not lastWordSelect_i)) then
                lastWordSelect_i <= wordSelect;

                if lastWordSelect_i = '1' then
                    currentSampleIndex_i <= (others => '0');
                end if;
            end if;

        end if;

        if falling_edge(serialClock) then
            if ((currentSampleIndex_i = "011100") or (currentSampleIndex_i = "111100")) then
                lastSample <= currentSample_i;
            end if;
        end if;

    end process;
end rtl;

transmisor.vhd 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

entity i2sTransmitter is
    port (
        serialClock     : in std_logic;
        wordSelect      : in std_logic;
        serialData      : out std_logic;
        lastSample      : in std_logic_vector(23 downto 0)
    );
end i2sTransmitter;

architecture rtl of i2sTransmitter is

    signal currentSample_i : std_logic_vector(23 downto 0) := (others => '0');
    signal currentSampleIndex_i : std_logic_vector(5 downto 0) := (others => '0');  
    signal lastWordSelect_i : std_logic;

begin

    process(serialClock)
    begin
        if rising_edge(serialClock) then

            currentSampleIndex_i <= std_logic_vector(unsigned(currentSampleIndex_i) + 1);

            if (lastWordSelect_i = (not lastWordSelect_i)) then         
                lastWordSelect_i <= wordSelect;
                if lastWordSelect_i = '1' then
                    currentSampleIndex_i <= "000001";
                end if;
            end if;
        end if;

        if falling_edge(serialClock) then
            if ((currentSampleIndex_i = "011100") or (currentSampleIndex_i = "111100")) then
                currentSample_i(23 downto 0) <= lastSample;
         end if;

            if currentSampleIndex_i(4 downto 0) < "11000" then
                serialData <= currentSample_i(to_integer(unsigned(currentSampleIndex_i(4 downto 0))));
            end if;
        end if;
    end process;

end rtl;

top.vhd 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity box is
    port(   
        clk                 : in std_logic;
        reset               : in std_logic;
        adcSerial       : in std_logic;
        mclkAdc         : out std_logic;
        sclkAdc         : out std_logic;
        lrclkAdc            : out std_logic;        
        dacSerial       : out std_logic;
        mclkDac         : out std_logic;
        sclkDac         : out std_logic;
        lrclkDac            : out std_logic     
    );
end box;

architecture Behavioral of box is

    component clk_wiz_v3_6 is
    port
    (
        clk_in1         : in std_logic;   
        mclk            : out std_logic;
        sclk             : out std_logic;     
        reset          : in std_logic
    );
    end component;

    component i2sClocks is
    port
    (
        clk             : in std_logic;
        lrclk           : out std_logic
    );
    end component;

    component i2sReceiver is
    port(
        serialClock     : in std_logic;
        wordSelect      : in std_logic;
        serialData      : in std_logic;
        lastSample      : out std_logic_vector(23 downto 0)
    );
    end component;

    component i2sTransmitter is
    port(
        serialClock     : in std_logic;
        wordSelect      : in  std_logic;
        serialData      : out std_logic;
        lastSample      : in std_logic_vector(23 downto 0)
    );
    end component;

    signal mclk_i   : std_logic;
    signal sclk_i   : std_logic;
    signal lrclk_i  : std_logic;

    signal dacSerial_i: std_logic;  

    signal sample_i : std_logic_vector(23 downto 0);

begin

    mclkAdc <= mclk_i;
    sclkAdc <= sclk_i;
    lrclkAdc <= lrclk_i;

    mclkDac <= mclk_i;
    sclkDac <= sclk_i;
    lrclkDac <= lrclk_i;

    dacSerial <= dacSerial_i;

    clocks: clk_wiz_v3_6
    port map
    (
        clk_in1 => clk,
        mclk => mclk_i,
        sclk => sclk_i,
        reset => reset
    );

    clocks2: i2sClocks
    port map
    (
        clk => sclk_i,
        lrclk => lrclk_i
    );      

    adc: i2sReceiver
    port map
    (
        serialClock => sclk_i,
      wordSelect => lrclk_i,
      serialData => adcSerial,
      lastSample => sample_i
    );

    dac: i2sTransmitter
    port map
    (
        serialClock => sclk_i,
      wordSelect => lrclk_i,
      serialData => dacSerial_i,
      lastSample => sample_i
    );



end Behavioral;

restricciones-limpieza.ucf 

CONFIG VCCAUX = "3.3" ;

NET "clk"           LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz;
NET "reset"         LOC = C17  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;

NET "dacSerial" LOC = T11;
NET "sclkDac"       LOC = T10;
NET "lrclkDac"      LOC = V13;
NET "mclkDac"       LOC = V11;

NET "adcSerial" LOC = H17;
NET "sclkAdc"       LOC = H18; 
NET "lrclkAdc"      LOC = J18;
NET "mclkAdc"       LOC = K16;

Resultados de la compilación

  1. Cuando el divisor de reloj de CORE Generator se conecta a las salidas (receptor), la síntesis y la implementación se realizan correctamente.

  2. Cuando el divisor de reloj de CORE Generator está conectado a las salidas del receptor y del transmisor, obtengo errores: 

    ERROR:ConstraintSystem:59 - Constraint <NET "sclkAdc"       LOC = H18;>
[constrains-clean.ucf(13)]: NET "sclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "sclkAdc"     LOC = H18;> [constrains-clean.ucf(13)]' could not be found
and so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <NET "mclkAdc"       LOC = K16;>
[constrains-clean.ucf(15)]: NET "mclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "mclkAdc"     LOC = K16;> [constrains-clean.ucf(15)]' could not be found
and so the Locate constraint will be removed.

  3. Cuando el divisor de reloj de CORE Generator está conectado a las salidas del receptor y del transmisor y al divisor adicional utilizado para generar LRCLK, obtengo errores: 

    ERROR:ConstraintSystem:59 - Constraint <NET "sclkAdc"       LOC = H18;>
[constrains-clean.ucf(13)]: NET "sclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "sclkAdc"     LOC = H18;> [constrains-clean.ucf(13)]' could not be found
and so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <NET "mclkAdc"       LOC = K16;>
[constrains-clean.ucf(15)]: NET "mclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "mclkAdc"     LOC = K16;> [constrains-clean.ucf(15)]' could not be found
and so the Locate constraint will be removed.

Done...

Checking expanded design ...

ERROR:NgdBuild:809 - output pad net 'sclkDac' has an illegal load:
pin C on block clocks2/i2sClocksDivider_i_0 with type FD,
pin C on block clocks2/i2sClocksDivider_i_1 with type FD,
pin C on block clocks2/i2sClocksDivider_i_2 with type FD,
pin C on block clocks2/i2sClocksDivider_i_3 with type FD,
pin C on block clocks2/i2sClocksDivider_i_4 with type FD,
pin C on block clocks2/i2sClocksDivider_i_5 with type FD,
pin C on block clocks2/i2sClocksDivider_i_6 with type FD

  4. Cuando el divisor de reloj de CORE Generator está conectado a las salidas del receptor y del transmisor, al divisor adicional utilizado para generar LRCLK y a los módulos I2S en el proyecto, obtengo errores: 

    WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "sclkAdc"     LOC = H18;> [constrains-clean.ucf(13)]' could not be found
and so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <NET "mclkAdc"       LOC = K16;>
[constrains-clean.ucf(15)]: NET "mclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "mclkAdc"     LOC = K16;> [constrains-clean.ucf(15)]' could not be found
and so the Locate constraint will be removed.

WARNING:NgdBuild:1012 - The constraint <NET "sclkAdc"       LOC = H18;>
[constrains-clean.ucf(13)] is overridden on the design object sclkDac by the
constraint <NET "sclkDac"       LOC = T10;> [constrains-clean.ucf(8)].

Para ser honesto, me pasé unos días tratando de resolverlo pero sin suerte. ¿Qué debo hacer para conectar correctamente el divisor de reloj de CORE Generator y crear un proyecto sin errores?

EDITAR:

Gracias a @Paebbels, las advertencias sobre wordSelect y currentSampleIndex_i_5 ya no se producen. Siguiendo sus consejos, cambié el diseño de la siguiente manera:

  1. Enrest.
  2. LOC = T10 | IOSTANDARD = LVCMOS33; tanto en el transmisor como en el receptor ahora se escribe sin firmar.
  3. currentSampleIndex y cada asignación o condición con ella se recorta a 5 bits
  4. La condición en el transmisor y el receptor ahora es currentSampleIndex

Errores fatales

Los errores y advertencias que ocurren durante la compilación son ahora como sigue:

  1. Cuando el divisor de reloj de CORE Generator está conectado a las salidas del receptor y del transmisor y al divisor adicional utilizado para generar LRCLK 

    Clock Information:
------------------
-----------------------------------+-----------------------------------+------        -+
Clock Signal                       | Clock buffer(FF name)             | Load  |
-----------------------------------+-----------------------------------+-------+
clocks/clk1obuf                    |         NONE(clocks2/i2sClocksDivider_i_0)| 7     |
clocks/pll_base_inst/CLKOUT1       |         BUFG                              | 1     |
clocks/pll_base_inst/CLKOUT0       |         BUFG                              | 1     |
-----------------------------------+-----------------------------------+------        -+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not
automatically buffered by XST with BUFG/BUFR resources. Please use
the buffer_type constraint in order to insert these buffers to the
clock signals to help prevent skew problems.


(...)

ERROR:ConstraintSystem:59 - Constraint <NET "sclkAdc"       LOC = H18 |>
[constrains-clean.ucf(13)]: NET "sclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "sclkAdc"     LOC = H18 |> [constrains-clean.ucf(13)]' could not be found
and so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33;>
[constrains-clean.ucf(13)]: NET "sclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <NET "mclkAdc"       LOC = K16 |>
[constrains-clean.ucf(15)]: NET "mclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "mclkAdc"     LOC = K16 |> [constrains-clean.ucf(15)]' could not be found
and so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33;>
[constrains-clean.ucf(15)]: NET "mclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

Done...

Checking expanded design ...
ERROR:NgdBuild:809 - output pad net 'sclkDac' has an illegal load:
pin C on block clocks2/i2sClocksDivider_i_0 with type FD,
pin C on block clocks2/i2sClocksDivider_i_1 with type FD,
pin C on block clocks2/i2sClocksDivider_i_2 with type FD,
pin C on block clocks2/i2sClocksDivider_i_3 with type FD,
pin C on block clocks2/i2sClocksDivider_i_4 with type FD,
pin C on block clocks2/i2sClocksDivider_i_5 with type FD,
pin C on block clocks2/i2sClocksDivider_i_6 with type FD

  2. Cuando el divisor de reloj de CORE Generator está conectado a las salidas del receptor y del transmisor, al divisor adicional utilizado para generar LRCLK y a los módulos I2S en el proyecto 

    INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_0> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_0> 
INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_1> in Unit <box> is equivalent to the following FF/Latch, which will be removed :       <dac/currentSampleIndex_us_1> 
INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_2> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_2> 
INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_3> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_3> 
INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_4> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_4> 
INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_5> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_5> 
INFO:Xst:2261 - The FF/Latch <adc/lastWordSelect_i> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/lastWordSelect_i> 

(...)


WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "sclkAdc"     LOC = H18 |> [constrains-clean.ucf(13)]' could not be found
and so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <NET "mclkAdc"       LOC = K16 |>
[constrains-clean.ucf(15)]: NET "mclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "mclkAdc"     LOC = K16 |> [constrains-clean.ucf(15)]' could not be found
and so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33;>
[constrains-clean.ucf(15)]: NET "mclkAdc" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.


WARNING:NgdBuild:1012 - The constraint <NET "sclkAdc"       LOC = H18 |>
[constrains-clean.ucf(13)] is overridden on the design object sclkDac by the
constraint <NET "sclkDac"       LOC = T10 |> [constrains-clean.ucf(8)].
WARNING:NgdBuild:1012 - The constraint <IOSTANDARD = LVCMOS33;>
[constrains-clean.ucf(13)] is overridden on the design object sclkDac by the
constraint <IOSTANDARD = LVCMOS33;> [constrains-clean.ucf(8)].
pregunta Peter

2 respuestas

1

Parece que los pines en su módulo superior no están de acuerdo con el archivo de restricciones.

    
respondido por el alex.forencich
1

Error en el archivo UCF: 

NET "reset" LOC = C17  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;

El pin reset es una entrada, por lo que no debe establecer una potencia de unidad de 8 mA y una tasa de giro, estas restricciones son para las salidas. Verifique su esquema, si el pin / cable de reinicio ya tiene una resistencia de extracción. Si es así, no habilite el pullup interno en la IOB.

También debe extender todas sus líneas con el estándar de E / S apropiado.

Simplificando el código VHDL: 

currentSampleIndex_i <= std_logic_vector(unsigned(currentSampleIndex_i) + 1);

Esta línea podría acortarse si declara currentSampleIndex_i como UNSIGNED .

  • Cláusula USE : use IEEE.NUMERIC_STD.all; (ya presente en su código)
  • Declaración: signal currentSampleIndex_us : UNSIGNED(5 downto 0) := (others => '0');
  • Recuento: currentSampleIndex_us <= currentSampleIndex_us + 1;
  • Comparaciones: if (currentSampleIndex_us = 5) then
  • Tipo de conversión: currentSampleIndex_i <= std_logic_vector(currentSampleIndex_us)

El tipo UNSIGNED es probablemente un STD_LOGIC_VECTOR , pero extendido con unsigned operaciones aritméticas como agregar, sub, mult, ... Si necesita firmado (2s complemento) la aritmética declara la señal como SIGNED .

La entrada ... nunca se usa :

  

ADVERTENCIA: Xst: 647 - Entrada < wordSelect > nunca se usa Este puerto se conservará y se dejará desconectado (...);

Entonces, el sintetizador le advierte que la señal wordSelect nunca se usa. Pero se usa en tu código / proceso. ¿Cómo puede suceder? Por ejemplo, si el flujo de control nunca llega a la línea lastWordSelect_i <= wordSelect; , entonces no se utilizará wordSelect.

Entonces, ¿por qué el flujo de control nunca llega a esta línea? Porque la condición (lastWordSelect_i = (not lastWordSelect_i)) nunca puede ser cierta. Puede volver a escribir la condición en (lastWordSelect_i != lastWordSelect_i) .

Solución : solucione esta condición.

El nodo ... de tipo secuencial no está conectado en el bloque ... :

  

ADVERTENCIA: Xst: 2677 - Nodo < currentSampleIndex_i_5 > de tipo secuencial no está conectado en el bloque < i2sReceiver >
  ADVERTENCIA: Xst: 2677 - Nodo < currentSampleIndex_i_5 > de tipo secuencial no está conectado en el bloque < i2sTransmitter >

Su señal currentSampleIndex_i tiene 6 bits. El sintetizador expande su vector a 6 cables separados llamados currentSampleIndex_i_0 a currentSampleIndex_i_5 . Se utilizan los bits 0 a 4, pero 5 es:

  • no utilizado o
  • tiene el mismo valor en cada ciclo o
  • no importa en las comparaciones.

Así que echemos un vistazo a las comparaciones ... 

-- condition 1 and 2
if ((currentSampleIndex_i             = "011100") or
    (currentSampleIndex_i             = "111100")) then
-- condition 3
     currentSampleIndex_i(4 downto 0) <  "11000"

Como puede ver, el bit 5 no importa.

Extenderé mi respuesta si encuentro más fallas ...

    
respondido por el Paebbels

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