Estoy diseñando un código VHDL para la operación de lectura y escritura en memoria

Estoy activando un código VHDL para leer y escribir en RAM. El código se adjunta como abajo,

library IEEE;   
use IEEE.STD_LOGIC_1164.ALL;    
use IEEE.STD_LOGIC_ARITH.ALL;    


entity RAM is
    port (address : in unsigned ( 127 downto 0); --- 128 bit address
            clk : in std_logic;
            data : inout std_logic_vector ( 7 downto 0);
            WE, CS, OE : in std_ulogic);      --- WE = write enable, CS = control signal, OE= output enable

            end entity RAM;

architecture RAM1 of RAM is
    subtype word_t is std_logic_vector(7 downto 0);    ---- 8 bit data width
    type memory_t is array( 127 downto 0) of word_t;    ---- 128 bit adress width
    signal RAMs : memory_t := (others => (others =>'z'));

        begin
            process (clk)
                begin
                    data <= (others => 'z');
                    if (CS = '0') then
                    data <= (others => 'z');
                    else if (CS = '1') then
                        if rising_edge (clk) then 
                            if ( WE='1' AND OE = '1') then                  ---- can not read and write at same time.
                                data <= '0';
                                else if ( WE='1' AND OE = '0') then
                                RAMs ( conv_integer(address'delayed)) <= data;
                                else if ( WE='0' AND OE = '1') then
                                data <= RAMs(conv_integer (address));
                                else if ( WE='1' AND OE = '1') then
                                data <= (others => 'z');
                            end if;
                        end if;
                    end if;
                end if;     
            end if;
        end if;
    end if;
end process;
end RAM1;

Cuando compilo este código, recibo un error como se muestra,