verilog traffic light system verilog

Tengo este sistema de semáforo de 4 vías

FSM

module FSM(HR, HY, HG, FR, FY, FG, ST, TS, TL, C, reset, Clk);
output HR;
output HY;
output HG;
output FR;
output FY;
output FG;
output ST;
input TS;
input TL;
input C;
input reset;
input Clk;
reg [6:1] state;
reg ST;

parameter highwaygreen = 6'b001100;
parameter highwayyellow = 6'b010100;
parameter farmroadgreen = 6'b100001;
parameter farmroadyellow = 6'b100010;
assign HR = state[6];
assign HY = state[5];
assign HG = state[4];
assign FR = state[3];
assign FY = state[2];
assign FG = state[1];

initial begin state = highwaygreen; ST = 0; end
always @(posedge Clk)
begin
if (reset)
begin state = highwaygreen; ST = 1; end
else
begin
ST = 0;
case (state)
highwaygreen:
if (TL & C) begin state = highwayyellow; ST = 1; end
highwayyellow:
if (TS) begin state = farmroadgreen; ST = 1; end
farmroadgreen:
if (TL | !C) begin state = farmroadyellow; ST = 1; end
farmroadyellow:
if (TS) begin state = highwaygreen; ST = 1; end
endcase
end
end
endmodule

TEMPORIZADOR

module Timer(TS, TL, ST, Clk);
output TS;
output TL;
input ST;
input Clk;
integer value;
assign TS = (value >= 4); // 5 cycles after reset
assign TL = (value >= 14); // 15 cycles after reset
always @(posedge ST) value = 0; // async reset
always @(posedge Clk) value = value + 1;
endmodule

TESTBENCH

module FSM_tb(
);

reg Clk, C, reset, TS, TL;
wire [6:1] state;
wire ST;

FSM DUT (.Clk(Clk), .reset(reset), .TS(TS), .TL(TL), .C(C), .ST(ST), 
.state(state));



initial
begin
    Clk = 0;
    forever
    begin
      #10 Clk = 1;
      #10 Clk = 0;
    end
end



initial
begin
  reset = 0; C = 0;;
#40 reset = 1;
#40 reset = 0;
#40 C = 1;
#40 C = 0;
#40 reset = 1;
#40 C = 1;
#40 C = 1;

  //details test IP stimuli
end

endmodule

Recibo este error cuando intento simular "no se permite la asignación de procedimientos a un ST que no está registrado, el lado izquierdo debe ser reg / integer / time / genvar".

¿Cómo resuelvo este error?