Soy novato en VHDL. En mi código, todo parece correcto pero el código no funciona correctamente. No pude encontrar dónde está mi culpa. ¿Alguna solución?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Knight_Rider is
port (
in_CLK: in std_logic;
out_LED: out std_logic_vector(9 downto 0)
);
end entity;
architecture Behavioral of Knight_Rider is
signal shift_reg: std_logic_vector (9 downto 0):= "0000000001";
signal counter: std_logic_vector (19 downto 0);
signal i: integer range 0 to 9;
signal res: std_logic:= '0';
begin
CLOCK:process(in_CLK)
begin
if(rising_edge(in_CLK )) then
counter <= counter + 1;
end if;
end process;
process(counter(19))
begin
if(rising_edge(counter(19)))then
if (res = '0') then
for i in 0 to 8 loop
shift_reg(i+1)<= shift_reg (i);
res <= '1';
end loop;
else
for i in 9 downto 1 loop
shift_reg(i-1) <=shift_reg(i);
res <= '0';
end loop;
end if;
end if;
end process;
out_LED <= shift_reg;
end architecture;
EDITAR: He cambiado el código un poco y ahora funciona perfectamente.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Karasimsek is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (9 downto 0));
end Karasimsek;
architecture Behavioral of Karasimsek is
signal shift_reg: STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
signal sayac: integer range 0 to 50000000;
signal yonsec: std_logic:= '0';
signal pulse: std_logic:= '0';
begin
process( CLK )
begin
if(rising_edge(CLK)) then
if (sayac < 50000000) then
sayac <= sayac + 1 ;
else
sayac <= 0;
pulse <= '1';
if (pulse = '1') then
if (yonsec = '0') then
shift_reg <= shift_reg (8 downto 0) & '0';
if (shift_reg(8) = '1') then
yonsec <= '1';
end if;
elsif (yonsec = '1') then
shift_reg <= '0' & shift_reg (9 downto 1);
if (shift_reg(1) = '1') then
yonsec <= not yonsec;
end if;
end if;
end if;
end if;
end if;
end process;
LED <= shift_reg;
end Behavioral;