En realidad, en mi proyecto vhdl, he incluido los bloques para generador de reloj, LSFR (generador de datos), IQ mapper, polifase. De todos estos bloques, el bloque polifásico de bloques falta por completo en la vista rtl. Es el problema en la técnica de codificación. En realidad estoy usando el factor de interpolación 32. Así que he creado 32 subfiltros como bloques en el componente polifásico. Si hay algún problema en este código a continuación, responda de inmediato.
este es el código para el componente polifásico y los componentes dentro de la polifase son subfiltros
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity polyphase is
Port ( clk : in STD_LOGIC;
clk_120mbps: in std_logic;
reset : in STD_LOGIC;
din : in STD_LOGIC_vector(7 downto 0);
ifiltout : out STD_LOGIC_vector(23 downto 0)
);
end polyphase;
architecture Behavioral of polyphase is
component subfilta
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
component subfiltb
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltc
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltd
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfilte
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltf
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltg
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfilth
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfilti
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
component subfiltj
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
component subfiltk
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltl
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltm
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
------
component subfiltn
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfilto
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltp
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
component subfiltq
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
component subfiltr
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfilts
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltt
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltu
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltv
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltw
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltx
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfilty
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
component subfiltz
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
component subfiltaa
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltbb
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltcc
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltdd
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltee
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltff
port( dout:out std_logic_vector(23 downto 0);
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
signal ifilterout0,ifilterout1,ifilterout2,ifilterout3:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout4,ifilterout5,ifilterout6,ifilterout7:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout8,ifilterout9,ifilterout10,ifilterout11:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout12,ifilterout13,ifilterout14,ifilterout15:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout16,ifilterout17,ifilterout18,ifilterout19:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout20,ifilterout21,ifilterout22,ifilterout23:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout24,ifilterout25,ifilterout26,ifilterout27:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout28,ifilterout29,ifilterout30,ifilterout31:STD_LOGIC_vector(23 downto 0):=(others =>'0');
--
begin
subfilt0a: subfilta port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout0);
subfilt0b: subfiltb port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout1);
subfilt0c: subfiltc port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout2);
subfilt0d: subfiltd port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout3);
subfilt0e: subfilte port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout4);
subfilt0f: subfiltf port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout5);
subfilt0g: subfiltg port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout6);
subfilt0h: subfilth port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout7);
subfilt0i: subfilti port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout8);
subfilt0j: subfiltj port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout9);
subfilt0k: subfiltk port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout10);
subfilt0l: subfiltl port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout11);
subfilt0m: subfiltm port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout12);
subfilt0n: subfiltn port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout13);
subfilt0o: subfilto port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout14);
subfilt0p: subfiltp port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout15);
subfilt0q: subfiltq port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout16);
subfilt0r: subfiltr port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout17);
subfilt0s: subfilts port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout18);
subfilt0t: subfiltt port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout19);
subfilt0u: subfiltu port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout20);
subfilt0v: subfiltv port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout21);
subfilt0w: subfiltw port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout22);
subfilt0x: subfiltx port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout23);
subfilt0y: subfilty port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout24);
subfilt0z: subfiltz port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout25);
subfilt0aa: subfiltaa port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout26);
subfilt0bb: subfiltbb port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout27);
subfilt0cc: subfiltcc port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout28);
subfilt0dd: subfiltdd port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout29);
subfilt0ee: subfiltee port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout30);
subfilt0ff: subfiltff port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout31);
--
P20:PROCESS(clk_120mbps,RESET)
VARIABLE CNT:STD_LOGIC_VECTOR(5 DOWNTO 0):="000000";
BEGIN
IF RESET='0' THEN
CNT:="000000";
ifiltout <=(others =>'0');
ELSIF clk_120mbps='1' AND clk_120mbps'EVENT THEN
CNT := CNT +1;
CASE CNT IS
WHEN "000001"=> ifiltout <=ifilterout0;
WHEN "000010"=> ifiltout <=ifilterout1;
WHEN "000011"=> ifiltout <=ifilterout2;
WHEN "000100"=> ifiltout <=ifilterout3;
WHEN "000101"=> ifiltout <=ifilterout4;
WHEN "000110"=> ifiltout <=ifilterout5;
WHEN "000111"=> ifiltout <=ifilterout6;
WHEN "001000"=> ifiltout <=ifilterout7;
WHEN "001001"=> ifiltout <=ifilterout8;
WHEN "001010"=> ifiltout <=ifilterout9;
WHEN "001011"=> ifiltout <=ifilterout10;
WHEN "001100"=> ifiltout <=ifilterout11;
WHEN "001101"=> ifiltout <=ifilterout12;
WHEN "001110"=> ifiltout <=ifilterout13;
----
WHEN "001111"=> ifiltout <=ifilterout14;
WHEN "010000"=> ifiltout <=ifilterout15;
WHEN "010001"=> ifiltout <=ifilterout16;
WHEN "010010"=> ifiltout <=ifilterout17;
WHEN "010011"=> ifiltout <=ifilterout18;
WHEN "010100"=> ifiltout <=ifilterout19;
WHEN "010101"=> ifiltout <=ifilterout20;
WHEN "010110"=> ifiltout <=ifilterout21;
WHEN "010111"=> ifiltout <=ifilterout22;
WHEN "011000"=> ifiltout <=ifilterout23;
WHEN "011001"=> ifiltout <=ifilterout24;
WHEN "011010"=> ifiltout <=ifilterout25;
WHEN "011011"=> ifiltout <=ifilterout26;
WHEN "011100"=> ifiltout <=ifilterout27;
WHEN "011101"=> ifiltout <=ifilterout28;
WHEN "011110"=> ifiltout <=ifilterout29;
WHEN "011111"=> ifiltout <=ifilterout30;
WHEN "100000"=> ifiltout <=ifilterout31;
--
--
CNT := "000000";
WHEN OTHERS => ifiltout <="000000000000000000000000";
END CASE;
--CNT <= CNT +1;
END IF;
END PROCESS P20;
end Behavioral;