Aquí está mi código para un contador n mod k en VHDL. Sigo recibiendo varios errores de sintaxis, pero parece que no puedo precisar exactamente lo que estoy haciendo mal. Cualquier ayuda sería apreciada.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity nmodkcounter is generic (
n : natural := 4;
k : natural := 10);
port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
load : in STD_LOGIC;
settime : in STD_LOGIC_VECTOR;
Q1 : out STD_LOGIC_VECTOR(n-1 downto 0);
Q2 : out STD_LOGIC_VECTOR(n-1 downto 0));
signal value : std_logic_vector(n-1 downto 0);
begin
PROCESS(clock, reset_n, load, k)
begin
if ((reset_n = ’0’) and (load = '0')) then --Resets LINE 22
value <= (OTHERS => ’0’); -- LINE 23
elsif (clock’event and clock = ’1’) --Counts up at rising edge LINE 24
then value <= (value + 1);
elsif (reset_n = '0' and load = '1') then --Sets time to loaded value
value <= settime;
end if;
if(value = k - 1) -- Resets count when value reaches k
then
Q1 <= '1'; -- Loads Q1 with 1 to send to next counter
value <= '0';
else
Q1 <= '0';
end if;
end process;
Q2 <= value; -- To output to display
end nmodkcounter;