Estoy usando Lattice Diamond, me pregunto cómo reconoce la celosía el tipo de señal al sintetizar vhdl / verilog.
Tengo un módulo como:
entity test is
PORT ( -- clk : in std_logic;
--rst : in std_logic;
bclk : in std_logic; -- burst clock
da : inout std_logic_vector(15 downto 0);
cs0_n : in std_logic; -- chipselect 0
cs1_n : in std_logic; -- chipselect 1
lba_n : in std_logic; -- address valid
eb : in std_logic_vector(3 downto 0); -- byte enable
rw_n : in std_logic; -- write enable (as seen from eim)
wait_n : out std_logic; -- wait (burst)
oe_n : in std_logic; -- read enable (as seen from eim)
dout : out std_logic
);
end entity test;
architecture behavioral of test is
...snip....
begin
-- the only time rw_n and lba_n appeared :
-- rw_n, lba_n recognized as clock, while cs0_n as regular port
da <= (others => 'Z') when cs0_n = '0' AND lba_n = '1' else data_out;
data_in <= da when rw_n = '0' AND lba_n = '1' else data_in;
...snip....
end
De alguna manera, Lattice sintetiza lba_n y rw_n como "Entrada de reloj" en la vista de hoja de cálculo. Esos no son relojes, deben definirse como puertos de entrada regulares.