ERROR: Xst: 827, Signal next_states1 no se puede sintetizar, mala descripción síncrona

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ERROR: Xst: 827 - "C: / Users / namec / Desktop / Class / VHDL / Traffic_Light / Traffic_lig‌ ht.vhd" línea 46: La señal next_states1 no se puede sintetizar, mala descripción síncrona. El estilo de descripción que está utilizando para describir un elemento síncrono (registro, memoria, etc.) no se admite en la versión actual del software.

Highway: process(CLk) 
    variable counter: integer := 0;    
begin
    case traffic_states1 is
        when H0 => 
            if (Input='0' and rising_edge(clk)) then 
                next_states1 <= H0;
                counter := counter + 1;
            elsif (counter <=20) and rising_edge(clk) then
                next_states1 <= H0;
                counter := counter + 1;
            elsif Input='1' and rising_edge(clk) and (counter >20) then
                next_states1 <= H1;
                counter := 0;
                -- else next_states1 <= traffic_states1;
            end if;
        when H1 =>     
            if counter = 3 and rising_edge(clk) then
                next_states1 <= H2;
                counter := 0;
            else
                next_states1 <= H1;
                counter := counter + 1;    
            end if;
        when H2 =>
            if rising_edge(clk) and counter = 9 then
                next_states1 <= H0;
                counter := 0;
            else
                next_states1 <= H2;
                counter := counter + 1;
            end if;
        when others =>
            null;