Tuve un problema en la simulación con mi señal de salida que se considera mi contador.
Aquí está mi código en vhdl:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Counter is
port (Clock, Reset : in std_logic;
Cpt : out std_logic_vector (3 downto 0) );
end Counter;
architecture archi of Counter is
signal s : std_logic_vector (3 downto 0);
begin
process (Clock, Reset)
begin
if Reset = '1' then
s <= "0000";
elsif (Clock='1' and Clock'event) then
s <= s + "1";
end if;
end process;
Cpt <= s;
end archi;
y aquí está mi test_bench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity tb_Counter is
end tb_Counter;
Architecture archi of tb_Counter is
component Counter is
port (Clock, Reset : in std_logic;
Cpt : out std_logic_vector (3 downto 0) );
end component;
signal Clock_sig : std_logic := '0';
signal Reset_sig : std_logic := '0';
signal Cpt_sig : std_logic_vector (3 downto 0);
begin
uut : Counter port map (Clock => Clock_sig, Reset => Reset_sig, Cpt => Cpt_sig);
stim: process
begin
--Reset_sig <= '0';
--Clock_sig <= '1';
Reset_sig <= '1';
wait for 10ns;
Reset_sig <= '0';
Clock_sig <= '1';
loop
wait for 10ns;
Clock_sig <= not Clock_sig;
end loop;
end process;
end archi;
Y aquí está mi resultado (con el error)
despuésdehacerunreinicioaquíestáelresultado