Estoy usando un FPGA Basys 3 con una memoria conectada y usando Vivado 2016.2. Mi objetivo es leer de 2 ^ 21 espacios de memoria de la RAM y enviar los datos a la computadora usando UART. Estoy usando un script MATLAB para capturar los datos seriales de UART. Pero, parece que mi código puede incrementar la dirección hasta 128 y leer datos de esas direcciones. Después de eso, la dirección se reinicia desde 0 y obtengo datos repetidos. Soy muy nuevo en VHDL y el código está escrito de forma ingenua. Supongo que el problema podría estar en el encasillado. La dirección que se comunica con la RAM es un std_logic_vector (20 downto 0). Pero, como necesitábamos incrementar la dirección en 1, hicimos ese incremento usando unsigned (20 downto 0) y luego escribimos s_rw_addr < = std_logic_vector (addr). [addr no tiene firma y s_rw_addr es std_logic_vector que se conectó a la RAM mediante puertos físicos].
Para resumir, MATLAB está recibiendo datos, pero los datos se repiten cada 128 veces. ¿Como puedó resolver esté problema?
-- ADDRESS CONTROLLER --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity control is
port (
clk: in std_logic;
rst: in std_logic;
u_rd_data: in std_logic_vector (7 downto 0);
u_rd_ready: in std_logic;
u_rd_clear: out std_logic;
u_wr_data: out std_logic_vector (7 downto 0);
u_wr_ready: in std_logic;
u_wr_start: out std_logic;
s_rw_addr: out std_logic_vector (20 downto 0);
s_rd_data: in std_logic_vector (7 downto 0);
s_wr_data: out std_logic_vector (7 downto 0);
s_rw_sel: out std_logic;
s_rw_start: out std_logic;
s_rw_ready: in std_logic
);
end control;
architecture arch of control is
type state_t is (
idle, clear, check_sram_rd_ready,
sram_read, sram_rd_ready, sram_read_done, uart_data_send, uart_send_wait, read_running,
sram_read_buf1, sram_read_buf2, sram_rd_ready_buf1, sram_rd_ready_buf2
);
signal state, n_state: state_t := idle;
--type data_t is array (0 to 3) of std_logic_vector (15 downto 0);
--signal data, n_data: data_t := (others => (others => '0'));
signal s_read_data, s_write_data: std_logic_vector (7 downto 0);
--signal dir, n_dir: std_logic;
signal i, n_i: unsigned (1 downto 0);
signal addr, n_addr: unsigned (20 downto 0):=(others => '0');
signal addr_increment: unsigned (20 downto 0):= (others => '0');
signal increment: unsigned (20 downto 0):= "000000000000000000001";
signal n_addr_increment: std_logic_vector (20 downto 0):= (others => '0');
signal read_write_selector, read_write_start: std_logic;
signal n_read_write_selector, n_read_write_start: std_logic;
begin
-- clock process
process (clk) is
begin
if (clk'event and clk = '1') then
state <= n_state;
data <= n_data;
dir <= n_dir;
i <= n_i;
addr <= n_addr;
--addr_increment <= n_addr_increment;
read_write_selector <=n_read_write_selector;
read_write_start <= n_read_write_start;
end if;
end process;
-- transition logic
process (state, u_rd_data, u_rd_ready, u_wr_ready, s_rd_data, s_rw_ready,
data, dir, i, addr, f, rst, read_write_selector,read_write_start ) is
begin
n_state <= state;
n_data <= data;
n_dir <= dir;
n_i <= i;
n_addr <= addr;
n_read_write_selector <=read_write_selector ;
n_read_write_start <= read_write_start;
case state is
when idle =>
if (u_rd_ready = '1') then
n_state <= clear;
end if;
u_wr_start <= '0';
when clear =>
if (u_rd_data= "00001111") then --u_rd_data = "11110000"
n_state <= sram_rd_ready;
n_i <= (others => '0');
n_addr <= "000000000000000000000";
addr_increment <= "000000000000000000000";
--n_addr <= addr_increment; --n_addr <= (others => '0')
else
n_state <= idle;
end if;
when sram_rd_ready =>
-- u_wr_start <= '0';
if (s_rw_ready = '1') then
n_state <= sram_read;
else
n_state <= check_sram_rd_ready;
end if;
when check_sram_rd_ready =>
n_state <= sram_rd_ready;
when sram_read =>
n_read_write_selector <= '0'; -- 0 for read, 1 for write
n_read_write_start <= '1'; -- 1 for start
n_state <= sram_read_buf1;
when sram_read_buf1 =>
if (s_rw_ready = '0') then
n_state <= sram_read_buf2;
else
n_state <= sram_read_done;
end if;
when sram_read_buf2 =>
-- n_read_write_start <= '0';
n_state <= sram_read_buf1;
when sram_read_done =>
n_read_write_start <= '0'; -- 0 for start
s_read_data <= s_rd_data;
n_state <= uart_data_send;
when read_running =>
n_state <= sram_read_done;
when uart_data_send =>
if (u_wr_ready = '1') then -----nik
u_wr_data <= s_read_data;------ niik
u_wr_start <= '1'; ---- nik
--if (addr_increment < "000000000000000001111") then
n_state <= sram_rd_ready_buf1;
--addr_increment <= std_logic(unsigned(n_addr)+1);
addr_increment <= n_addr + increment; --- n_addr in bracket
--addr <= addr_increment;
--addr_increment <= n_addr_increment;
--u_wr_start <= '0';
--else
--u_wr_start <= '1';
--n_state <= idle;
-- u_rd_clear <='1';
-- end if;
--u_rd_clear <='1';
else
n_state <= uart_send_wait;
end if;
when uart_send_wait =>
n_state <= uart_data_send;
when sram_rd_ready_buf1 =>
-- if (u_wr_ready = '0') then
n_state <= sram_rd_ready_buf2;
n_addr <= addr_increment;
-- else
-- n_state <= sram_rd_ready;
-- n_addr <= addr_increment;
-- end if;
when sram_rd_ready_buf2 =>
n_state <= sram_rd_ready;
end case;
end process;
s_rw_addr <= std_logic_vector(addr) ;--(addr);
s_rw_sel <= read_write_selector;
s_rw_start <= read_write_start;
--n_addr <= addr_increment;
end arch;
-- BASYS3 TOP MODULE --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity basys3_top is
port (
clk: in std_logic;
btnC: in std_logic;
btnU: in std_logic;
uart_txd: out std_logic;
uart_rxd: in std_logic;
sram_data: inout std_logic_vector (7 downto 0);
sram_addr: out std_logic_vector (20 downto 0);
sram_wr, sram_rd: out std_logic;
sram_en: out std_logic;
seg_an: out std_logic_vector (3 downto 0);
led: out std_logic_vector (15 downto 0)
);
end basys3_top;
architecture arch of basys3_top is
signal u_rd_ready, u_rd_clear: std_logic;
signal u_wr_ready, u_wr_start: std_logic;
signal u_rd_data, u_wr_data: std_logic_vector (7 downto 0);
signal clk1 : std_logic;
signal s_rw_addr: std_logic_vector (20 downto 0);
signal s_rd_data, s_wr_data: std_logic_vector (7 downto 0);
signal s_rw_sel, s_rw_start, s_rw_ready: std_logic;
--signal sram_en, sram_wr, sram_rd: std_logic;
-- signal sram_addr: std_logic_vector (20 downto 0);
-- signal sram_data: std_logic_vector (7 downto 0);
signal db_btnC, db_btnU: std_logic;
component clk_wiz_0 is
port (
clk_out1 : out std_logic;
clk_in1 : in std_logic
);
end component clk_wiz_0;
begin
uVGA_CLK : clk_wiz_0
port map (
clk_out1 => clk1,
clk_in1 => clk
);
uart_control: entity work.uart_control
port map ( clk1, db_btnC, u_rd_data, u_rd_ready, u_rd_clear, u_wr_data, u_wr_ready, u_wr_start,
uart_txd, uart_rxd );
control: entity work.control
port map ( clk1, db_btnC, u_rd_data, u_rd_ready, u_rd_clear, u_wr_data, u_wr_ready, u_wr_start,
s_rw_addr, s_rd_data, s_wr_data, s_rw_sel, s_rw_start, s_rw_ready );
sram_control: entity work.sram_control
port map ( clk1, db_btnC, s_rw_addr, s_rd_data, s_wr_data, s_rw_sel, s_rw_start, s_rw_ready,
sram_en, sram_wr, sram_rd, sram_addr, sram_data );
debouncer0: entity work.debouncer
port map ( clk, btnC, db_btnC );
debouncer1: entity work.debouncer
port map ( clk, btnU, db_btnU );
seg_an <= (others => '1'); -- prevent light from leaking current under floating signals
led <= "00000000" & sram_data; --& sram_addr (4 downto 0); -- & sram_en & sram_wr & sram_rd &
-- sram_data <= (others => 'Z');
end arch;