La adición del divisor de frecuencia no causa salida de VHDL

Estoy tratando de obtener la salida de este código. La salida no se muestra después de agregar el divisor de frecuencia. Antes del divisor de frecuencia, el código funcionaba bien y mostraba la salida.

Este es mi código

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ASM_combine is
port(clk,rst, A, B,DOOR: in std_logic;
    Z:buffer std_logic_vector(1 downto 0);
    out1,out2,out3:out std_logic_vector(0 to 6));
end ASM_combine;

architecture structure of ASM_combine is
component divide_by_25M is
port( clk: in std_logic;
clk_out: out std_logic);
end component;

component ASM is
port(clk, rst, A, B,DOOR: in std_logic;
    Z:buffer std_logic_vector(1 downto 0));
end component;

component bcd_7segment 
port( BCD:in std_logic_vector(1 downto 0);
 decoder_out: out std_logic_vector(0 to 6));
end component;

component bcd_7segment2 
port( BCD:in std_logic_vector(1 downto 0);
decoder_out: out std_logic_vector(0 to 6));
end component;

component bcd_7segment3 
port( BCD:in std_logic_vector(1 downto 0);
decoder_out: out std_logic_vector(0 to 6));
end component;

signal c: std_logic;

begin
U0:divide_by_25M port map (clk=>clk, clk_out=>c);
U1: ASM port map(clk=>c, rst=>rst, A=>A, B=>B,DOOR=>DOOR, Z=>Z);
U2: bcd_7segment port map(BCD(0)=>Z(0),BCD(1)=>Z(1),decoder_out=>out1);
U3: bcd_7segment2 port map(BCD(0)=>Z(0),BCD(1)=>Z(1),decoder_out=>out2);
U4: bcd_7segment3 port map(BCD(0)=>Z(0),BCD(1)=>Z(1),decoder_out=>out3);
end structure;

Testbench:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ASM_combine_tb is
end ASM_combine_tb;

architecture behave of ASM_combine_tb is
component ASM_combine
port(clk,rst, A, B,DOOR: in std_logic;
    Z:buffer std_logic_vector(1 downto 0);
    out1,out2,out3:out std_logic_vector(0 to 6));
end component;

signal clk: std_logic :='0';
signal rst : std_logic:='1';
signal A,B,DOOR: std_logic:='0';
signal out1,out2,out3: std_logic_vector(0 to 6);
signal Z: std_logic_vector(1 downto 0);
constant clk_period: time := 200ns;

begin
uut: ASM_combine port map 
(clk=>clk,rst=>rst,A=>A,B=>B,DOOR=>DOOR,Z=>Z,
out1=>out1,out2=>out2,out3=>out3);

clk_process:process
begin
clk<='0';
wait for clk_period/2; 
clk<='1';
wait for clk_period/2;
end process;

-- Stimulus process
stimulus: process
begin     
rst<='0' after 100 ns;
DOOR<='1' after 1800 ns;

A<='1';
B<='0';
wait until rising_edge(clk); wait for 1 ps;
A<='1';
B<='0';
wait until rising_edge(clk); wait for 1 ps;
A<='0';
B<='0';
wait until rising_edge(clk); wait for 1 ps;
A<='1';
B<='0';
wait until rising_edge(clk); wait for 1 ps;
A<='1';
B<='1';
wait until rising_edge(clk); wait for 1 ps;
end process;
end behave;