Debe realizar la máquina Mealy en la memoria integrada (VHDL)

Necesito ayuda para realizar la maquina Mealy en emb. Ahora tengo un código de trabajo para la máquina Moore. Cómo hacer que Miles funcione, de acuerdo con las señales de control

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;

entity emb_mile is
    port(
         clk : in std_logic;
         we : in STD_LOGIC;
         addr : in STD_LOGIC_VECTOR(3 downto 0);
         di : in STD_LOGIC_VECTOR(4 downto 1);
         do : out STD_LOGIC_VECTOR(4 downto 1)
         );
end emb_mile;

--}} End of automatically maintained section

architecture emb_mile of emb_mile is
type ram_type is array (12 downto 0) of std_logic_vector (4 downto 1);
signal RAM : ram_type:=(
    "0000","0000","0000","0000","0000","1000","0010","0011","0001","0000","0000","0000","0000"
    );
begin

    process (clk)
    begin
        if rising_edge(clk) then
            if we = '1' then
                RAM(conv_integer(addr)) <= di;
            end if;
            do <= RAM(conv_integer(addr));
        end if;
    end process;

     -- enter your statements here --

end emb_mile;