banco de pruebas VHDL para registro de desplazamiento con carga paralela

Mi problema es el siguiente: intenté escribir el banco de pruebas VHDL para el registro de desplazamiento con carga paralela en HDL activo. La forma de onda es buena hasta que la parte de carga paralela no quiere cargar p en q. ¿Por qué? ¿Alguien podría ayudar un poco?

library ieee;
use ieee.std_logic_1164.all;

-- Add your library and packages declaration here ...

entity shiftregister_tb is
end shiftregister_tb;

architecture TB_ARCHITECTURE of shiftregister_tb is
-- Component declaration of the tested unit
component shiftregister
port(
    d : in std_logic;
    p : in std_logic_vector(3 downto 0);
    clk : in std_logic;
    clr : in std_logic;
    load : in std_logic;
    q : inout std_logic_vector(3 downto 0) );
end component;

-- Stimulus signals - signals mapped to the input and inout ports of   tested entity
signal d : std_logic;
signal p : std_logic_vector(3 downto 0);
signal clk : std_logic;
signal clr : std_logic;
signal load : std_logic;
signal q : std_logic_vector(3 downto 0);   
constant clk_period:time :=10 ns;
-- Observed signals - signals mapped to the output ports of tested entity



begin

-- Unit Under Test port map
UUT : shiftregister
    port map (
        d => d,
        p => p,
        clk => clk,
        clr => clr,
        load => load,
        q => q
    );



clk_process :process
begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
end process;


  -- Stimulus process
  stim_proc: process
  begin     
    d<='0';
    wait for 10 ns; 
    d<='1';
    wait for 10 ns;
    d<='0'; 
    wait for 10 ns; 
    d<='0'; 
    wait for 10 ns; 
    clr<='1';
    wait for 10 ns;
    clr<='0';
    d<='0';
    wait for 10 ns; 
    d<='1';
    wait for 10 ns;
    d<='1'; 
    wait for 10 ns; 
    d<='1';  
    wait for 10 ns;
    clr<='1';
    wait for 10 ns;
    load<='1';
    p<="0011";
end process;

END;




configuration TESTBENCH_FOR_shiftregister of shiftregister_tb is
for TB_ARCHITECTURE
    for UUT : shiftregister
        use entity work.shiftregister(behavior);
    end for;
end for;
end TESTBENCH_FOR_shiftregister;