declaración concurrente ilegal

0

Realmente no tengo idea de por qué este código es incorrecto.

** Error: F:/midterm night/assg 3/mem/mux8_1.vhd(12): Illegal concurrent statement.
** Error: F:/midterm night/assg 3/mem/mux8_1.vhd(22): VHDL Compiler exiting



library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
entity mux8_1 is 
port( q0,q1,q2,q3,q4,q5,q6,q7: in  std_logic_vector ( 15 downto 0);
  addr : in std_logic_vector ( 2 downto 0);
  dout : out std_logic_vector (15 downto 0));
end entity;
architecture mux_arch of mux8_1 is
begin
case addr is 
when "001" => dout <= q1;   
when "010" => dout <= q2;
when "011" => dout <= q3;
when "100" => dout <= q4;
when "101" => dout <= q5;
when "110" => dout <= q6;
when "111" => dout <= q7; 
when others => dout <= q0;
end case;
end mux_arch;
    
pregunta m.rizk

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