Necesito ayuda con las instancias de componentes (mapas de puertos) en VHDL. Tengo un sumador completo de 16 bits que quiero importar en mi ALU, y debería activarse cuando el opcode se vuelva "000". En el siguiente código que tengo, Sum y Carry no estarán definidos después de usar el testbench. Tomé ayuda de aquí para implementar el mapa del puerto. Tal vez no esté usando el banco de pruebas correctamente aquí.
FullAdder16Bit.vhd :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity FullAdder16Bit is
port(A,B: in std_logic_vector(15 downto 0);
Cin: in std_logic;
Sum: out std_logic_vector(15 downto 0);
Cout: out std_logic);
end FullAdder16Bit;
architecture behavior of FullAdder16Bit is
begin
process(A,B,Cin)
variable carry: std_logic;
begin
carry:=Cin;
for i in 0 to 15 loop
carry:=(A(i) and B(i)) or (carry and (A(i) or B(i)));
end loop;
sum<=A + B + Cin;
Cout<=carry;
end process;
end behavior;
ALU16Bit.vhd :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity arith is
port(A,B: in std_logic_vector(15 downto 0);
opcode: in std_logic_vector(2 downto 0);
Sum: out std_logic_vector(15 downto 0);
Carry: out std_logic;
mult: buffer std_logic_vector(31 downto 0));
end arith;
architecture rtl of arith is
component FullAdder16Bit is
port(A,B: in std_logic_vector(15 downto 0);
Cin: in std_logic;
Sum: out std_logic_vector(15 downto 0);
Cout: out std_logic);
end component;
signal areg,breg,sreg:std_logic_vector(15 downto 0);
signal cinreg,coutreg:std_logic;
begin
Add: FullAdder16Bit port map(A=>A,B=>B,Cin=>'0',Sum=>Sum,Cout=>Carry);
process(A,B,opcode)
begin
Sum<=(others=>'0');
Carry<='0';
mult<=(others=>'0');
case opcode is
when "000" =>
areg<=A; breg<=b;cinreg<='0'; Sum<=sreg; Carry<=coutreg;
when others =>
Sum<=(others=>'Z');
Carry<='Z';
mult<=(others=>'Z');
end case;
end process;
end rtl;
tb_ALU16Bit.vhd :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_arith is
end tb_arith;
architecture structure of tb_arith is
component arith is
port(A,B: in std_logic_vector(15 downto 0);
opcode: in std_logic_vector(2 downto 0);
Sum: out std_logic_vector(15 downto 0);
Carry: out std_logic;
mult: buffer std_logic_vector(31 downto 0));
end component;
signal A,B,Sum: std_logic_vector(15 downto 0);
signal Carry: std_logic;
signal opcode: std_logic_vector(2 downto 0);
signal mult: std_logic_vector(31 downto 0);
begin
DUT: arith port map(A,B,opcode,Sum,Carry,mult);
process
begin
wait for 0 ns;
opcode<="000";
A<="0000111111111111";
B<="1111111111111111";
wait for 10 ns;
opcode<="001";
A<="0000111111111111";
B<="1111111111111111";
wait;
end process;
end structure;
configuration tb_arith_con of tb_arith is
for structure
end for;
end tb_arith_con;