¿Dónde debo incluir la creación de instancias en el módulo superior (contador)

0

Estoy haciendo un módulo de contador en la placa Basys-2. Esta es mi instanciación del circuito de desmontaje

 debouncing U0(
.clock(clock),
.reset(reset),
.button(button),
.out(out)
 );

Pero estoy recibiendo un error en Xilinx 14.7 como

ADVERTENCIA: Xst: 646 - La señal se asigna pero nunca se usa. Esta señal desconectada se recortará durante el proceso de optimización. ADVERTENCIA: Xst: 1290 - El bloque jerárquico está desconectado en el bloque.    Será eliminado del diseño.

Si es que tengo que incluir esta creación de instancias en el módulo contador, ¿dónde debería y por qué recibo este error?

Counter Circuit
module button_binary(
input clock,
input reset,
input button,
output led,
output led2,
output led3,
output led4,
output led5,
output led6,
output led7,
output led8
);

reg [7:0]count;

  always @ (posedge clock or posedge reset)
  begin
 if (reset)
    count <= 0;
else if (button)
    count <= count + 1;
end

assign led = count[0];
assign led2 = count[1];
assign led3 = count[2];
assign led4 = count[3];
assign led5 = count[4];
assign led6 = count[5];
assign led7 = count[6];
assign led8 = count[7];
endmodule 

// Módulo de debouncing

module debouncing(
input clock,
input reset,
input button,
output reg out
);

localparam N = 19;        //for a 10ms tick
reg [N-1:0]count;
wire tick; 

//the counter that will generate the tick.

always @ (posedge clock or posedge reset)
 begin
    if(reset)
        count <= 0;
    else
        count <= count + 1;        
 end

 assign tick = &count;        //AND every bit of count with itself. Tick will only go high when all 19 bits of count are 1, i.e. after 10ms

 // now for the debouncing FSM

 localparam[2:0]                     //defining the various states to be used
            zero = 3'b000, 
            high1 = 3'b001,
            high2 = 3'b010,
            high3 = 3'b011,
            one = 3'b100,
            low1 = 3'b101,
            low2 = 3'b110,
            low3 = 3'b111;

reg [2:0]state_reg;
reg [2:0]state_next;

always @ (posedge clock or posedge reset)      
 begin
    if (reset)
        state_reg <= zero;
    else
        state_reg <= state_next;
end


always @ (*)
 begin
    state_next <= state_reg;  // to make the current state the default state
    out <= 1'b0;                    // default output low

    case(state_reg)
        zero:
            if (button)                    //if button is detected go to next state high1
                state_next <= high1;
        high1:
            if (~button)                //while here if button goes back to zero then input is not yet stable and go back to state zero
                state_next <= zero;
            else if (tick)                //but if button remains high even after 10 ms, go to next state high2.
                state_next <= high2;
        high2:
            if (~button)                //while here if button goes back to zero then input is not yet stable and go back to state zero
                state_next <= zero;
            else if (tick)                //else if after 20ms (10ms + 10ms) button is still high go to high3
                state_next <= high3;
        high3:
            if (~button)                //while here if button goes back to zero then input is not yet stable and go back to state zero
                state_next <= zero;
            else if (tick)                //and finally even after 30 ms input stays high then it is stable enough to be considered a valid input, go to state one
                state_next <= one;

        one:                                //debouncing eliminated make output high, now here I'll check for bouncing when button is released
            begin
                out <= 1'b1;
                    if (~button)        //if button appears to be released go to next state low1
                        state_next <=  low1;
            end
        low1:
            if (button)                //while here if button goes back to high then input is not yet stable and go back to state one
                state_next <= one;
            else if (tick)            //else if after 10ms it is still high go to next state low2
                state_next <= low2;
        low2:
            if (button)                //while here if button goes back to high then input is not yet stable and go back to state one
                state_next <= one;
            else if (tick)            //else if after 20ms it is still high go to next state low3
                state_next <= low3;
        low3:
            if (button)                //while here if button goes back to high then input is not yet stable and go back to state one
                state_next <= one;
            else if (tick)            //after 30 ms if button is low it has actually been released and bouncing eliminated, go back to zero state to wait for next input.
                state_next <= zero;
        default state_next <= zero;

    endcase
  end
endmodule
    
pregunta raghav

1 respuesta

1

El mensaje de error le indica que hay una señal (un wire net) que solo está "conectada" en un extremo; no tiene sentido definir un cable con una fuente pero sin carga, o una carga pero sin carga fuente. Por lo general, este es el resultado de no declarar explícitamente la red.

Suponiendo que pretende que su módulo superior conecte el puerto de salida .out de una instancia debouncing al puerto de entrada .button de un módulo button_binary , entonces su módulo superior tendrá un aspecto similar al siguiente:

// Toplevel module ports connect to external FPGA pins
module top (
    input clock,
    input reset,
    input button,
        output led,
        output led2,
        output led3,
        output led4,
        output led5,
        output led6,
        output led7,
        output led8
);

// Declare the wire net that will connect your modules
wire buttonDebounced; //!< driven by inst_debouncing1

// Instantiate the debouncing module 
debouncing inst_debouncing1(
        .clock(clock), //!< external input pin
        .reset(reset), //!< external input pin
        .button(button), //!< from physical button to be debounced
                .out(buttonDebounced) //!< debounced switch output
    );

// Instantiate the button_binary module
button_binary inst_button_binary1(
        .clock(clock), //!< external input pin
        .reset(reset), //!< external input pin
        .button(buttonDebounced), //!< driven by inst_debouncing1
            .led(led), //!< external output pin
            .led2(led2), //!< external output pin
            .led3(led3), //!< external output pin
            .led4(led4), //!< external output pin
            .led5(led5), //!< external output pin
            .led6(led6), //!< external output pin
            .led7(led7), //!< external output pin
            .led8(led8), //!< external output pin
    );

endmodule
    
respondido por el MarkU

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