¿Cómo eliminar la distancia relativa entre las cuatro ondas sinusoidales ruidosas retardadas y comenzarlas desde el principio?

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Estamos intentando generar una señal de onda sinusoidal ruidosa, que se cambiará de fase tres veces para generar las señales s1, s2, s3 y s4. Para ello, hemos creado una matriz sine2 que retendrá la señal de onda sinusoidal ruidosa, y la cambiaremos según nuestra conveniencia cambiando su índice.

El problema es por qué s1, s2, s3, s4 no empiezan desde el principio (es decir, desde t = 0). y por qué hay brechas relativas entre la señal como se ve en la figura. Necesitamos eliminar ese espacio y, si es posible, iniciarlo desde t = 0. Por favor ayuda. 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;  --try to use this library as much as possible.

entity sine_wave is
 generic ( width : integer :=  4 ); 
port (clk :in  std_logic;
      random_num : out std_logic_vector (width-1 downto 0); 
      data_outa,data_outb,data_outc,data_outd : out STD_LOGIC_VECTOR(7 downto 0)
      );
end sine_wave;

architecture Behavioral of sine_wave is
signal data_out1,rand_temp1,noisy_signal,data_outb1,data_outc1,data_outd1, summation_signal : integer;
signal noisy_signal1,s1,s2,s3,s4 : STD_LOGIC_VECTOR(7 downto 0);
signal summation_signal1 : STD_LOGIC_VECTOR(11 downto 0);
signal i : integer :=0;
signal j : integer :=120;
signal k : integer :=40;
signal l : integer :=80;
signal ii,iii: integer :=0 ;
signal jj: integer :=30 ;
signal kk: integer :=60 ;
signal ll: integer :=90 ;
--type memory_type is array (0 to 29) of integer;
type memory_type is array (0 to 359) of std_logic_vector(7 downto 0); 
signal sine2 : memory_type;
--ROM for storing the sine values generated by MATLAB.
signal sine : memory_type :=(x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"01",
x"01",x"01",x"01",x"01",x"02",x"02",x"02",x"02",x"03",x"03",
x"03",x"04",x"04",x"04",x"04",x"05",x"05",x"05",x"05",x"06",
x"06",x"07",x"07",x"08",x"08",x"09",x"09",x"0a",x"0a",x"0b",
x"0b",x"0c",x"0c",x"0d",x"0d",x"0e",x"0e",x"0f",x"0f",x"10",
x"11",x"11",x"12",x"13",x"13",x"14",x"15",x"15",x"16",x"17",
x"18",x"18",x"19",x"1a",x"1b",x"1b",x"1c",x"1d",x"1e",x"1e",
x"1f",x"20",x"21",x"22",x"23",x"23",x"24",x"25",x"26",x"27",
x"28",x"29",x"2a",x"2b",x"2c",x"2d",x"2f",x"2f",x"30",x"31",
x"32",x"34",x"35",x"35",x"36",x"37",x"38",x"39",x"3a",x"3b",
x"3c",x"3c",x"3e",x"3f",x"40",x"41",x"42",x"43",x"44",x"45",
x"46",x"46",x"47",x"48",x"49",x"49",x"4a",x"4b",x"4c",x"4c",
x"4e",x"4f",x"4f",x"50",x"51",x"51",x"52",x"53",x"53",x"54",
x"55",x"55",x"56",x"57",x"57",x"58",x"58",x"59",x"59",x"5a",
x"5a",x"5b",x"5b",x"5c",x"5c",x"5d",x"5d",x"5e",x"5e",x"5f",
x"5f",x"5f",x"60",x"60",x"60",x"61",x"61",x"61",x"61",x"62",
x"62",x"62",x"62",x"63",x"63",x"63",x"63",x"63",x"63",x"64",
x"64",x"64",x"64",x"64",x"64",x"64",x"64",x"64",x"64",x"64",
x"64",x"64",x"64",x"64",x"64",x"64",x"63",x"63",x"63",x"63",
x"63",x"63",x"62",x"62",x"62",x"62",x"61",x"61",x"61",x"60",
x"60",x"60",x"5f",x"5f",x"5f",x"5e",x"5e",x"5d",x"5d",x"5c",
x"5c",x"5b",x"5b",x"5a",x"5a",x"59",x"59",x"58",x"58",x"57",
x"57",x"56",x"55",x"55",x"54",x"54",x"53",x"53",x"52",x"51",
x"51",x"50",x"4f",x"4f",x"4e",x"4d",x"4c",x"4c",x"4b",x"4a",
x"49",x"49",x"48",x"47",x"46",x"46",x"45",x"44",x"44",x"43",
x"42",x"41",x"41",x"40",x"3f",x"3e",x"3d",x"3c",x"3c",x"3b",
x"3a",x"39",x"38",x"37",x"36",x"35",x"35",x"34",x"33",x"32",
x"31",x"30",x"2f",x"2f",x"2e",x"2d",x"2c",x"2b",x"2a",x"29",
x"28",x"28",x"27",x"26",x"25",x"24",x"23",x"23",x"22",x"21",
x"20",x"1f",x"1e",x"1e",x"1d",x"1c",x"1b",x"1b",x"1a",x"19",
x"18",x"18",x"17",x"16",x"15",x"15",x"14",x"13",x"13",x"12",
x"11",x"11",x"10",x"0f",x"0f",x"0e",x"0d",x"0d",x"0c",x"0c",
x"0b",x"0b",x"0a",x"0a",x"09",x"09",x"08",x"08",x"07",x"07",
x"06",x"06",x"05",x"05",x"05",x"04",x"04",x"04",x"03",x"03",
x"03",x"02",x"02",x"02",x"02",x"01",x"01",x"01",x"01",x"01",
x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00");
--hi
begin

process(clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';
begin
  --to check the rising edge of the clock signal
if(rising_edge(clk)) then  

temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;

--data_out <= sine(i);
i <= i+ 1;
if(i = 359) then
i <= 0;
end if;

j <= j+ 1;
if(j = 359) then
j <= 0;
end if;

k <= k+ 1;
if(k = 359) then
k <= 0;
end if;

l <= l+ 1;
if(l = 359) then
l <= 0;
end if;

data_outa <= sine(i);

data_outb <= sine(j);
data_outc <= sine(k);
data_outd <= sine(l);


random_num <= rand_temp;
rand_temp1<=to_integer(unsigned(rand_temp));
data_out1<=to_integer(unsigned(sine(i)));
noisy_signal<=data_out1+rand_temp1;
noisy_signal1<= std_logic_vector(to_signed(noisy_signal,8));
--data_outb1 <= to_integer(unsigned(sine(j)));
--data_outc1 <= to_integer(unsigned(sine(k)));
--data_outd1 <= to_integer(unsigned(sine(l)));
--summation_signal <= data_outb1+data_outc1+data_outd1+noisy_signal;
--summation_signal1 <= std_logic_vector(to_signed(summation_signal,12));

--for ii in 0 to 359 loop
--   sine2(ii)<=noisy_signal1;
--   s1 <= sine2(ii);   
--  end loop;

sine2(ii)<=noisy_signal1;
     ii <= ii+ 1;
         if(ii = 359) then
         ii <=0;
         end if;

     s1 <= sine2(iii);
     iii <= iii+ 1;
     if(iii = 359) then
     iii <= 0;
     end if;

    s2 <= sine2(jj);
    jj <= jj+ 1;
    if(jj = 359) then
    jj <= 0;
    end if;
     s3 <= sine2(kk);
     kk <= kk+ 1;
     if(kk = 359) then
     kk <= 0;
     end if;
     s4 <= sine2(ll);
     ll <= ll+ 1;
     if(ll = 359) then
     ll <= 0;
     end if;

end if;
--data_outa <= sine(i);

--data_outb <= sine(j);
--data_outc <= sine(k);
--data_outd <= sine(l);

--data_out1<=to_integer(unsigned(sine(i)));
--random_num <= rand_temp;
--rand_temp1<=to_integer(unsigned(rand_temp));
--noisy_signal<=data_out1+rand_temp1;
--noisy_signal1<= std_logic_vector(to_signed(noisy_signal,8));
----data_outb1 <= to_integer(unsigned(sine(j)));
----data_outc1 <= to_integer(unsigned(sine(k)));
----data_outd1 <= to_integer(unsigned(sine(l)));
----summation_signal <= data_outb1+data_outc1+data_outd1+noisy_signal;
----summation_signal1 <= std_logic_vector(to_signed(summation_signal,12));

----for ii in 0 to 359 loop
----     sine2(ii)<=noisy_signal1;
----     s1 <= sine2(ii);   
----    end loop;

end process;



end Behavioral;

    
pregunta Anwesa Roy

1 respuesta

1

Los puntos de inicio diferentes aparentes son un artefacto de simulación causado porque sine2 no se está inicializando y diferentes salidas de onda sinusoidal que utilizan diferentes puntos de inicio en la tabla sine2. Los cuatro generadores obtienen datos válidos en diferentes momentos. Antes de eso, los valores de sine2 serían "UUUUUUUU" s.

La idea aquí es mantener alejadas las salidas s1, s2, s3 y s4 hasta que sine2 se haya cargado completamente una vez.

Hay una señal agregada para indicar cuando sine2 se ha cargado completamente una vez: 

signal ll: integer := 90;

signal ii_gate: std_logic := '0';  -- ADDED signal

type memory_type is array (0 to 359) of std_logic_vector(7 downto 0); 
signal sine2:  memory_type;

Luego en el proceso: 

        sine2(ii) <= noisy_signal1;

        ii <= ii + 1;
        if ii = 359 then
            ii <= 0;
            ii_gate <= '1';  -- set ii_gate when sine2 has been written once
        end if;

        if ii_gate = '1' then  -- use ii_gate to hold off s1,s2,s3 and s4

            s1 <= sine2(iii);
            iii <= iii + 1;
            if iii = 359 then
                iii <= 0;
            end if;

            s2 <= sine2(jj);
            jj <= jj + 1;
            if jj = 359 then
                jj <= 0;
            end if;

            s3 <= sine2(kk);
            kk <= kk + 1;
            if kk = 359 then
                kk <= 0;
            end if;

            s4 <= sine2(ll);
            ll <= ll + 1;
            if ll = 359 then
                ll <= 0;
            end if;
        end if;
    end if;   -- rising_edge(clk)

La señal ii_gate retiene la salida de s1, s2, s3 y s4 hasta que sine2 se haya cargado una vez eliminando los valores de 'U' en las búsquedas en la tabla sine2. Podría contemplar los efectos de la memoria sin inicializar sine2 en el inicio en un FPGA.

La especificación de diseño modificada da:

y muestra las cuatro formas de onda que muestran datos válidos al mismo tiempo. Tenga en cuenta que las diferencias de fase son visibles en la forma de onda.

Un banco de pruebas para el diseño: 

library ieee;
use ieee.std_logic_1164.all;

entity sine_wave_tb is
end entity;

architecture foo of sine_wave_tb is
    constant WIDTH:     integer :=   4; 
    signal clk:         std_logic := '0';
    signal random_num:  std_logic_vector (WIDTH - 1 downto 0); 
    signal data_outa,
           data_outb,
           data_outc,
           data_outd:   std_logic_vector (7 downto 0);
begin
CLOCK:
    process
    begin
        wait for 50 ns;
        clk <= not clk;
        if now > 500 us then
            wait;
        end if;
    end process;

DUT:
    entity work.sine_wave
        generic map (WIDTH => WIDTH)
        port map (
            clk => clk,
            random_num => random_num,
            data_outa => data_outa,
            data_outb => data_outb,
            data_outc => data_outc,
            data_outd => data_outd
        );
end architecture;

También comenté en su pregunta que indica que el agregado para el valor inicial de rand_temp no se puede representar de conformidad con el estándar VHDL usando un agregado con un índice estático no local y otra opción.

También cambié eso: 

begin

    process(clk)
        variable rand_temp:  std_logic_vector(WIDTH - 1 downto 0) 
                    -- := (WIDTH - 1 => '1', others => '0');
                    := ('1', others => '0');
        variable temp:  std_logic :=  '0';
    begin

Ver IEEE Std 1076-2008, 9.3.3.3 Agregados de arreglos, párrafos 6 y 7 que especifican la limitación.

El uso de la asociación posicional evita el problema al asegurar el cumplimiento de las normas y la portabilidad de las especificaciones de diseño.

Si alguien lo informa como un error, se podría solucionar.

    
respondido por el user8352

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